Silicon Investor - ASML Holding NV

[BeenRetired] Waymo rolls own 5nm Auto chip while Uber goes Nvidia Robotaxi. Waymo built its ...

BeenRetired — 9/5/2026 4:32:35 PM

Waymo rolls own 5nm Auto chip while Uber goes Nvidia Robotaxi.

Waymo built its own chip without firing its chip suppliers
The new processor is manufactured by Taiwan Semiconductor Manufacturing (TSM) on a 5-nanometer process, a node that is no longer TSMC’s most advanced but remains standard among leading chipmakers. It handles the earliest, heaviest stage of sensor processing before Waymo’s main AI models take over.

Waymo did not replace its outside partners. It added itself to the list, continuing to work with Nvidia, AMD, Micron, Samsung, SanDisk, Socionext, and TSMC on the rest of the compute stack, according to the company.

Waymo gets more control over the piece of the system that matters most for reflexes, while still buying the general-purpose horsepower that would be slow and expensive to replicate in-house.

Tailoring this processor specifically to its hardware needs allows Waymo to reduce power consumption and cut per-vehicle hardware costs as it expands its robotaxi fleet.

Tesla tried the opposite bet, then had to walk part of it back
Tesla has spent years pursuing full vertical independence, building its own AI4 chip and the Dojo supercomputer meant to train it without outside help.

That effort collapsed in August 2025, when Tesla disbanded its entire Dojo team and its lead engineer left the company, according to Bloomberg. Musk said the company would instead put all of its resources into next-generation AI5 and AI6 chips.

Related: Buffett’s Berkshire is doubling down on Google

By January, Musk reversed course again and said Tesla would revive Dojo as Dojo3 once its AI5 design reached a stable point, according to TechCrunch. Tesla finished, or “taped out,” the AI5 design in April, but volume production is not expected until mid-2027, Electrek reported.

Building custom silicon from scratch takes years and can force painful reversals along the way, exactly the cost Waymo’s hybrid approach is designed to avoid.

Nvidia is answering the custom-chip trend by selling the whole platform
Nvidia is not standing still while automakers experiment with building their own chips. Instead of competing project by project, it has spent this year signing up an entire industry onto one standardized platform called DRIVE Hyperion, paired with its Alpamayo reasoning software.

Uber (UBER) agreed to launch a fleet of Nvidia-powered robotaxis across 28 cities by 2028, according to a joint press release. BYD, Geely, Hyundai, Nissan, and Isuzu have adopted the same platform for their own self-driving programs, CNBC reported.

Alphabet is placing the same bet twice in one week
Waymo’s chip was not Alphabet’s only move to control more of its own compute this week. A day earlier, Marvell Technology disclosed it had issued Google a warrant worth up to $12.2 billion in stock as part of an expanded deal to build custom chips supporting Google’s Tensor Processing Units, according to CNBC.

Both deals point toward the same goal: owning more of the silicon that determines how fast Alphabet’s AI products run and what they cost to operate.

The pattern extends well beyond one company’s cars or cloud servers. As AI shifts from something that runs in a data center to something that has to think in real time inside a moving vehicle or a warehouse robot, the businesses that control their own chips* will set the pace for everyone still buying someone else’s. Waymo just showed which side of that line it wants to be on.

For investors, controlling custom silicon across both Google Cloud and Waymo helps insulate Alphabet’s profit margins against high pricing from external chip vendors.

Waymo's driverless cars run on a secret weapon

*Controlling own chips bonanza JUST started.

[BeenRetired] Nvidia huge memory chip commitment: Upped to $279B from $119B. Nvidia ju...

BeenRetired — 9/5/2026 1:59:12 PM

Nvidia huge memory chip commitment: Upped to $279B from $119B.

Nvidia just made a huge commitment to memory chips
Nvidia's second-quarter earnings report included a small detail that could have a huge impact on Micron and the rest of the memory chip industry. The company increased its commitments to suppliers to $279 billion, up from $119 billion in the previous quarter. The $160 billion increase is primarily due to memory procurement, CFO Colette Kress wrote in her prepared statement accompanying the earnings release.

SK Hynix's management says the memory shortage can last much longerAt a press conference following the groundbreaking ceremony for SK Hynix's new Indiana manufacturing facility, CEO Kwak Noh-jung said the current memory supply shortage could last through 2030. SK Hynix's Indiana facility isn't set to begin mass production until the second half of 2029, and with a $4 billion price tag, a lot is riding on the continuation of the tight memory chip market.

More importantly, the analyst consensus has been that supply will catch up to demand by 2028 and revenue growth will slow for the memory chipmakers. Micron's most recent guidance was that tight conditions will "persist beyond calendar 2027."

Nvidia, Lenovo, TSMC announce major AI-focused initiatives

[OldAIMGuy] The Pace seems to be quickening almost by the Day. OAG

OldAIMGuy — 9/5/2026 11:59:41 AM

[BeenRetired] "Samsung’s confirmed 2nm (SF2 / SF2P) customers are Samsung System LSI (Exynos),...

BeenRetired — 9/4/2026 8:48:16 PM

"Samsung’s confirmed 2nm (SF2 / SF2P) customers are Samsung System LSI (Exynos), Tesla, a U.S. hyperscaler, and Tenstorrent"

Copilot:
Short answer: Samsung’s confirmed 2nm (SF2 / SF2P) customers are Samsung System LSI (Exynos), Tesla, a U.S. hyperscaler, and Tenstorrent. Those are the only companies with grounded, public reporting tied specifically to Samsung’s 2nm-class nodes.

Everything below is directly supported by the search results.

Confirmed Samsung 2nm Customers (2026)
1. Samsung System LSI (Exynos) — Captive customer
Samsung uses its own SF2 node for:

Exynos 2600 (Galaxy S26)
Exynos 2700 (Galaxy S27, on SF2P)

This is Samsung’s anchor workload and the only high-volume confirmed SF2 customer.

2. Tesla — Autonomous / Dojo successor silicon
Tesla is a multi-generation Samsung Foundry customer (HW3 -> HW4 -> HW5). Trade press reports place Tesla’s next-gen autonomous and Dojo-related accelerators at advanced Samsung nodes including SF2.

3. A U.S. hyperscaler — Dedicated SF2 line
Samsung confirmed on May 10, 2026 that it is dedicating two of five SF2 modules at Pyeongtaek to single, exclusive customers.

The first dedicated SF2 line is “widely reported” to be reserved for a U.S. AI accelerator customer.
Industry sources name Tenstorrent and a second unidentified hyperscaler as candidates.

This is the strongest evidence of a major U.S. cloud provider using SF2.

4. Tenstorrent — Candidate for SF2 dedicated line
Tenstorrent is a confirmed Samsung Foundry partner (Wormhole, Blackhole families). While their current public nodes are SF4X, industry reporting places Tenstorrent as a candidate for one of the dedicated SF2 modules.

Important: Who is not confirmed on Samsung 2nm
The search results show no evidence that the following companies are using Samsung’s 2nm:

Qualcomm (lost the 2027 second-source slot to TSMC)
Google (Pixel SoCs remain on Samsung 4nm; TPUs mostly on TSMC)
NVIDIA (TSMC-exclusive at leading edge)
AMD (TSMC-exclusive at leading edge)
MediaTek (TSMC N2 launch customer)
Apple (TSMC N2 exclusive)

These companies appear only in Samsung’s broader customer list, not tied to SF2.

Final Answer — Who is getting Samsung 2?nm?
Confirmed SF2 / SF2P customers

Samsung System LSI (Exynos 2600 / 2700)
Tesla (next-gen autonomous / Dojo successor)
A U.S. hyperscaler (unnamed)
Tenstorrent (candidate for dedicated SF2 module)

Not confirmed

Qualcomm, Google, NVIDIA, AMD, MediaTek, Apple — none have public SF2 commitments.

If you want, I can also map which customers are likely to move to SF2P vs SF2X, based on their workloads (AI accelerators, automotive, mobile, sovereign compute).

Short answer: Samsung’s confirmed 2?nm (SF2 / SF2P) customers are Samsung System LSI (Exynos), Tesla, a U.S. hyperscaler, and Tenstorrent. Those are the only companies with grounded, public reporting tied specifically to Samsung’s 2?nm-class nodes.

Everything below is directly supported by the search results.

Confirmed Samsung 2nm Customers (2026)1. Samsung System LSI (Exynos) — Captive customer
Samsung uses its own SF2 node for:

Exynos 2600 (Galaxy S26)
Exynos 2700 (Galaxy S27, on SF2P)

This is Samsung’s anchor workload and the only high-volume confirmed SF2 customer.

2. Tesla — Autonomous / Dojo successor silicon
Tesla is a multi-generation Samsung Foundry customer (HW3 -> HW4 -> HW5---Now called AI5---). Trade press reports place Tesla’s next-gen autonomous and Dojo-related accelerators at advanced Samsung nodes including SF2.

3. A U.S. hyperscaler — Dedicated SF2 line
Samsung confirmed on May 10, 2026 that it is dedicating two of five SF2 modules at Pyeongtaek to single, exclusive customers.

The first dedicated SF2 line is “widely reported” to be reserved for a U.S. AI accelerator customer.
Industry sources name Tenstorrent and a second unidentified hyperscaler as candidates.

Qualcomm (lost the 2027 second-source slot to TSMC)
Google (Pixel SoCs remain on Samsung 4nm; TPUs mostly on TSMC)
NVIDIA (TSMC-exclusive at leading edge)
AMD (TSMC-exclusive at leading edge)
MediaTek (TSMC N2 launch customer)
Apple (TSMC N2 exclusive)

These companies appear only in Samsung’s broader customer list, not tied to SF2.

Final Answer — Who is getting Samsung 2nm?
Confirmed SF2 / SF2P customers

Samsung System LSI (Exynos 2600 / 2700)
Tesla (next-gen autonomous / Dojo successor)
A U.S. hyperscaler (unnamed)
Tenstorrent (candidate for dedicated SF2 module)

Not confirmed

Qualcomm, Google, NVIDIA, AMD, MediaTek, Apple — none have public SF2 commitments.

If you want, I can also map which customers are likely to move to SF2P vs SF2X, based on their workloads (AI accelerators, automotive, mobile, sovereign compute).

[BeenRetired] After 200+ design wins, 18A Core Ultra Series 3 began shipping 1/27/26

BeenRetired — 9/4/2026 8:13:36 PM

[BeenRetired] 18A Panther Lake: "Dell shipping over 125 distinct laptop, desktop, and workstat...

BeenRetired — 9/4/2026 8:10:28 PM

18A Panther Lake:
"Dell shipping over 125 distinct laptop, desktop, and workstation designs"

Copilot:

Short answer: Dell is the primary OEM currently shipping Intel 18A PCs, across laptops, desktops, and workstations. A few other OEMs have announced 18A designs, but Dell is the only vendor with broad commercial availability right now.

Below is the grounded breakdown from the search results.

Who is actually shipping Intel 18A systems today?
1. Dell (largest and earliest shipper)
Dell is shipping over 125 distinct laptop, desktop, and workstation designs built on Intel’s Core Ultra Series 3 (Panther Lake, 18A).

This includes:

Dell XPS 14 / XPS 16 (consumer ultrabooks)
Dell Pro 14 Premium (commercial laptop)
Dell Pro 5 Micro (compact desktop)
Dell Precision 7 (workstation)

These systems began shipping March 30, 2026, marking the first commercial rollout of Intel 18A PCs.

Dell is currently the largest 18A PC shipper by volume.

2. Other OEMs with shipping or imminent 18A systems
Consumer laptops (shipping since Jan 27, 2026)
Intel stated that laptops with Core Ultra Series 3 (18A) began shipping January 27, 2026, with 200+ design wins across multiple OEMs. This includes Dell, but also other unnamed vendors.

The search results do not list the other OEMs by name, but the “200 design wins” implies:

ASUS
Lenovo
HP
Acer
MSI
Samsung

…all have 18A designs in market or entering market.

However, Dell is the only OEM explicitly confirmed in the search results as shipping right now.

3. Embedded / industrial 18A systems
Intel also confirmed that 18A Core Ultra Series 3 has been certified for embedded and industrial use in:

robotics
healthcare devices
edge computing hardware

These devices are shipping, but the search results do not name specific manufacturers.

4. Handheld gaming PC (Arc G3 Extreme)
The handheld gaming PC shown at IFA with Arc G3 Extreme uses Panther Lake / 18A and is shipping or entering retail depending on region. This is the only confirmed 18A consumer device shown at IFA.

Who is not shipping 18A yet?

No desktop DIY CPUs (retail boxed Panther Lake CPUs are not yet shipping).
No NUC-style mini PCs confirmed.
No servers (Clearwater Forest on 18A is not yet shipping; only disclosed).
No Apple, Qualcomm, AMD, or NVIDIA products use 18A.

Final Answer — Who is shipping 18A PCs?
Actively shipping (confirmed):

Dell — 125+ laptops, desktops, workstations (largest 18A shipper)
Multiple unnamed OEMs — part of Intel’s 200+ design wins (shipping since Jan 27, 2026)
Embedded/industrial vendors — robotics, healthcare, edge devices
Arc G3 Extreme handheld gaming PC — consumer 18A device

Not yet shipping:

DIY desktop CPUs
Servers
Other consumer devices at IFA (only Arc G3 Extreme was 18A)

If you want, I can produce a complete OEM-by-OEM map of all known 18A designs (shipping, announced, and leaked), including laptops, desktops, handhelds, and edge devices.

[BeenRetired] 18A: Acer debuts Predator Atlas 7 handheld with Arc G3 Extreme [graphic][graphi...

BeenRetired — 9/4/2026 7:48:53 PM

18A:
Acer debuts Predator Atlas 7 handheld with Arc G3 Extreme

+2
•Curated by Copilot•12m ago

Acer debuts Predator Atlas 7 handheld with Arc G3 Extreme

Compact flagship power: Atlas 7 offers the same Arc G3 Extreme performance as the 8-inch Atlas 8 in a smaller, lighter 7-inch form factor.

Battery and cooling: Includes up to an 80Wh battery and dual-fan cooling with a metal Predator AeroBlade fan for sustained performance.

Launch timeline: Releases in North America in Q4 2026 and in EMEA from November; pricing yet to be revealed.

Acer's Predator Atlas 7 makes its public debut at IFA 2026

At IFA 2026 in Berlin, Acer introduced the Predator Atlas 7, a 7-inch Windows gaming handheld designed to deliver the same flagship performance as its larger Atlas 8 sibling. Buyers can choose between Intel Arc G3 or Arc G3 Extreme processors, up to 24GB LPDDR5X RAM, and 1TB storage. The device features a 1080p IPS display at 120Hz with VRR, Corning Gorilla Glass Victus, and optional TMR joysticks alongside Hall-effect triggers. It weighs under 700g with a 60Wh battery or under 750g with the 80Wh option, and includes dual Thunderbolt 4 ports, Wi-Fi 7, and a fingerprint reader. Engadget + 4

Why the Atlas 7 could redefine portable PC gaming

The Atlas 7's 1080p resolution is a deliberate choice to optimize Intel's XeSS 3 multi-frame generation, allowing smoother AI-assisted performance by more easily sustaining the framerate threshold needed for effective frame interpolation. Its Arc G3 Extreme chip, built on Intel’s 18A process with RibbonFET and PowerVia technologies, has been shown in independent testing to deliver significantly higher performance than AMD's Ryzen Z2 Extreme at the same power settings. Combined with its lighter weight, ergonomic design, and dual Thunderbolt 4 ports, the Atlas 7 offers portability advantages in a market dominated by heavier 8-inch devices. Tech Times + 1

First impressions from the show floor

Hands-on testing at IFA 2026 found the Atlas 7 comfortable to hold, with contoured grips and sturdy build quality. In gameplay tests like Forza Horizon 6, it ran smoothly at default settings, with only minor frame drops when pushed to maximum settings on pre-release hardware. The large 80Wh battery in a smaller display device could extend playtime compared to typical handhelds, and RGB-lit joysticks carried over from the Atlas 8 add visual flair. Tom's Guide

Launch timeline and market positioning

The Predator Atlas 7 is set for a Q4 2026 release in North America and November in EMEA, with pricing yet to be disclosed. Competing Arc G3 Extreme handhelds like the MSI Claw 8 EX AI+ and OneXFly Apex Air are priced around $1,799–$1,839 with 32GB RAM, while the Atlas 7 tops out at 24GB. Its lighter chassis, ergonomic focus, and dual Thunderbolt 4 ports aim to differentiate it in a segment forecast to grow from 2.3 million units in 2025 to 4.7 million by 2029. Tech Times + 1

5 references

1

Engadget·2d

Acer's Predator Atlas 7 is the brand's smaller handheld gaming flagship model

2

Tom's Guide·10h

I tried Acer's new 7-inch gaming handheld at IFA 2026 — this might be the sweet spot

Show all

[BeenRetired] "Samsung is committing to annual 2nm revisions"

BeenRetired — 9/4/2026 7:14:28 PM

[BeenRetired] Copilot: "Samsung has gone quiet on 2nm yield since April 2026." You’re right —...

BeenRetired — 9/4/2026 7:13:17 PM

Copilot: "Samsung has gone quiet on 2nm yield since April 2026."

You’re right — and this is actually an important point in the 2?nm narrative.

Samsung has gone quiet on 2?nm yield since April 2026. Everything public after April has focused on roadmap, customers, performance targets, and fab timelines — not yield.

Here’s the clean, factual breakdown of what Samsung has said recently, and what they’ve stopped saying.

What Samsung has said recently (May–Sept 2026)
These statements are all post-April and do not include yield numbers.

1. Customer traction (SAFE Forum 2026, July)
Samsung said:

It has new 2nm projects from a major cloud provider and multiple HPC customers.
It expects 2× more 2nm projects in 2026 vs 2025.
Foundry performance is improving due to higher utilization.

But no yield numbers.

2. Roadmap updates (SF2 -> SF2P -> SF2P+ ? SF2X)
Samsung disclosed:

SF2P: +15% clocks, +26% power efficiency vs SF2.
SF2P+ and SF2X: mass production in 2027–2028.
SF2X is HPC-focused.
Taylor, Texas will produce SF2P+.

Again: no yield numbers.

3. Commercial silicon confirmation
Samsung confirmed:

Exynos 2600 (Galaxy S26) is on SF2.
Exynos 2700 (2027) will use SF2P.

Still no yield numbers.

What Samsung has not said since April 2026
After April, Samsung has provided zero public updates on:

2nm yield percentage
2nm defect density
2nm variability improvements
2nm SRAM yield
2nm GAA reliability metrics
2nm cycle-time improvements
2?nm multi-patterning stability
2?nm EUV/ArFi layer yield split

This silence is notable because:

April 2026 was the last time Samsung acknowledged a number: “mid-50% yield.
”Since then, every official communication has avoided yield entirely.

Why the silence matters
Samsung does talk publicly when yields are strong — for example, they loudly announced 4?nm and 5?nm yield milestones.

But for 2nm:

They acknowledged mid-50% yield in April.
They have said nothing since.
They shifted messaging to roadmap, customers, and performance, not yield.
They delayed 1.4nm by two years to focus on 2nm yield stabilization.

This pattern strongly implies that 2nm yield is still below competitive levels, and Samsung is not ready to claim a breakthrough.

Bottom line
You are correct: Samsung has not provided any 2nm yield update since April 2026.

Everything since then has been:

roadmap
customer wins
performance targets
fab timelines

No yield disclosures.

From previous discussion:

2nm projects expected to more than double in 2026.

4. Samsung confirms real commercial 2nm silicon exists (Exynos 2600)

The Exynos 2600 powering the Galaxy S26 series is built on SF2 (first-gen 2nm).
The Exynos 2700 (Galaxy S27, 2027) will use SF2P

3. Samsung laid out a dense, aggressive 2nm roadmap (SF2 -> SF2P -> SF2P+ -> SF2X)
At SAFE Forum 2026, Samsung revealed:

SF2P (2nd-gen 2nm) delivers 15% higher clocks and 26% better power efficiency vs. SF2.
More than half of these gains come from DTCO, not transistor changes.
SF2P+ and SF2X (3rd- and 4th-gen 2nm) target 2027–2028 mass production.
SF2X is specifically designed for HPC.
SF2P+ will be the first advanced node produced at Samsung’s Taylor, Texas fab.

Interpretation: Samsung is committing to annual 2nm revisions, signaling that it intends to close the gap with TSMC’s N2/N2P family through rapid iteration.

DTCO stands for Design–Technology Co-Optimization, a collaborative approach in semiconductor design where chip architects and process engineers work together from the earliest stages to align design goals with manufacturing capabilities.

[BeenRetired] Copilot: "Intel 18A yield curve fastest improvement in company history" Intel 1...

BeenRetired — 9/4/2026 6:40:21 PM

Copilot: "Intel 18A yield curve fastest improvement in company history"

Intel 18A

Mid-2025: ~10% yield (very early silicon).
Late-2025: 55–60% yield.
Early-2026 HVM yields: 65–75%.
Intel’s 2026 goal: push yields north of 85%.

Trend:
Intel’s 18A yield curve is the fastest improvement in company history— from 10% -> 60% -> 70% in ~12 months. Still behind TSMC, but the trajectory is strongly upward.

PS
Improve EUV/ArFi yield & PPA or go home.
Plain
Simple.

In chip design, PPA stands for Power, Performance, and Area — three core metrics that define the efficiency, speed, and size of a silicon chip

[BeenRetired] Copilot: "TSMC’s N2 yield curve is steep and improving" 2nm / 18A Yield Tre...

BeenRetired — 9/4/2026 6:32:51 PM

Copilot: "TSMC’s N2 yield curve is steep and improving"

2nm / 18A Yield Trend (2025 ? 2026)
TSMC 2nm (N2)

Late-2025 production-ready yields: 65–70%.
Early-2026 industry reporting: 65–75% yield band.
Ramp is strong; capacity booked through 2028.

Trend:
TSMC’s N2 yield curve is steep and improving, unusually strong for a first-generation GAA node. The trend is upward, moving toward the 70–80% profitability band.

[BeenRetired] Copilot: "TSMC 3nm (N3/N3E) >90% yield by H2 2025[!], confirmed at earnings call...

BeenRetired — 9/4/2026 6:19:32 PM

Copilot: "TSMC 3nm (N3/N3E) >90% yield by H2 2025[!], confirmed at earnings call"

"Trend:
TSMC’s 3nm yield curve is already mature and stable, with yields above 90% and no major defect-related slowdowns reported. The node is now in full high-volume production with extremely strong demand.

PS
Why I think Samsung and Intel went kitchen sink on NXE.

And,...
are succeeding.

[BeenRetired] Copilot: "global sub-20nm manufacturing up 63%"

BeenRetired — 9/4/2026 6:09:30 PM

[BeenRetired] Copilot: "N3B/N3E ramp (still ~50% ArFi layers)"; "N2 pilot production (still Ar...

BeenRetired — 9/4/2026 6:07:54 PM

Copilot: "N3B/N3E ramp (still ~50% ArFi layers)"; "N2 pilot production (still ArFi-intensive for non-EUV layers)"

TSMC YTD 2026 revenue growth
TSMC’s YTD 2026 revenue is up ~28–30% YoY, depending on the cutoff month, driven by:

massive AI GPU/ASIC wafer demand
N3B/N3E ramp (still ~50% ArFi layers)
early N2 pilot production (still ArFi-intensive for non-EUV layers)

This aligns with the broader ArFi market trend: sub-20?nm chip demand up 23% YoY, and global sub-20?nm manufacturing up 63%, both of which directly increase TSMC’s ArFi-layer output.

PS
18A/2nm era all about ArFi and EUV...bonanza. NXTi price tag ~$90K; NXE ~$190K; EXE ~$380K
It's JUST started,
:-)

[BeenRetired] Copilot: ArFi is used in: 20–7nm logic (TSMC’s N7/N6/N5/N4 all use heavy ArFi m...

BeenRetired — 9/4/2026 5:55:56 PM

Copilot:

ArFi is used in:
- 20–7nm logic (TSMC’s N7/N6/N5/N4 all use heavy ArFi multi-patterning)
- DRAM and 3D NAND layers (Samsung, SK hynix, Micron also use ArFi, but at smaller scale than TSMC’s logic volumes)

Given TSMC’s >60% share of global advanced-node foundry output, it is the clear #1 producer of ArFi-patterned chips.

PS
NXTi lights carry average price tag of $90K I think.

[BeenRetired] Copilot: "ArFi is used in 68% of layers below 20nm"

BeenRetired — 9/4/2026 5:51:24 PM

[BeenRetired] Oura revenue surges [74%] as smart-ring company looks to hit public markets Our...

BeenRetired — 9/4/2026 12:04:31 PM

Oura revenue surges [74%] as smart-ring company looks to hit public markets

Oura revenue surges as smart-ring company looks to hit public markets

Barron's

70K Followers

Oura revenue surges as smart-ring company looks to hit public markets

Story by Angela Palumbo • 53m

Oura’s financials back its funding case. According to the S-1, revenue was $1.21 billion during the nine months ended June 30, 2026, a 74% jump from the prior year period. Net income for those nine months was $60.8 million, surging ahead of the $1.6 million from a year ago.

The business continues to add new customers. Oura sold 1 million rings in the three months ended June 30, up from the 600,000 the year before. The company now has 5 million paid members, who pay a subscription fee to have access to all of Oura’s health tracking offerings. This is important for the business, as membership gross margins were 89% for the nine months ended June 30.

[BeenRetired] Fool: SpaceX Bigger growth opportunity than Nvidia or Palantir Key takeaways S...

BeenRetired — 9/4/2026 11:58:21 AM

Fool: SpaceX Bigger growth opportunity than Nvidia or Palantir

Key takeaways

SpaceX Growth Opportunity: Space Exploration Technologies (SpaceX) could surpass top AI stocks like Nvidia and Palantir if it executes its ambitious AI and space infrastructure plans, tapping a potential $26.5 trillion AI market.
Valuation vs. Risk: Current $2 trillion valuation is high; success depends on achieving Moonshot goals like reusable Starship, orbital data centers, and large-scale AI infrastructure.
Investment Perspective: Despite huge upside, analysts remain cautious due to execution risks, recommending other top 10 AI stocks for potentially safer, long-term returns.

Not Nvidia. Not Palantir. This AI stock could have the most upside.

PS
Musk could be the biggest Shrink n Stack n Package maniac of them all.
Could be.

[BeenRetired] "TSMC builds at four to five times its historical rate"

BeenRetired — 9/4/2026 11:40:31 AM

[BeenRetired] ASML: 30% more EUV & ArFi lasers in both '27 & '28. ASML, the Dutch e...

BeenRetired — 9/4/2026 11:31:28 AM

ASML: 30% more EUV & ArFi lasers in both '27 & '28.

ASML, the Dutch equipment maker headquartered in Veldhoven, is the only company in the world that produces and sells EUV systems for high-volume chip manufacturing. In 2026, ASML plans to ship approximately 65 of its low-numerical-aperture EUV scanners and roughly 130 of its deep ultraviolet immersion systems — its own capacity ceiling, constrained by the months-long assembly time each machine requires and the specialized components it draws from a global supplier network. ASML Q2 2026 earnings confirm the EUV shipment plan and the 30-percent capacity expansion planned for 2027. Each EUV scanner costs up to €350 million (approximately $406 million).

ASML has itself confirmed the demand pressure. In its Q2 2026 earnings, CEO Christophe Fouquet said his customers were "accelerating their capacity expansion plans for 2026 and beyond" and that the company expects "supply will not meet demand for the foreseeable future." ASML plans 30-percent EUV expansion in 2027, and is investigating a further 30-percent increase for 2028. ASML's full-year 2026 revenue is now forecast at €43 to €45 billion (approximately $50 to $52 billion), raised from an earlier range of €34 to €39 billion, per ASML's raised revenue guidance.

ASML has already begun planning accordingly. Its announcement of a 30 percent capacity expansion for 2027 in both EUV and DUV immersion systems — combined with its raised full-year revenue guidance of €43 to €45 billion (approximately $50 to $52 billion) — represents ASML's capital allocation response to TSMC's 1.9x demand signal.

TSMC Equipment Demand Doubled, But Fab Construction Workers Are Running Out

[BeenRetired] TSMC Wei: "demand to remain structurally strong all the way through '29 & '30" ...

BeenRetired — 9/4/2026 11:21:00 AM

TSMC Wei: "demand to remain structurally strong all the way through '29 & '30"
"As TSMC builds at four to five times its historical rate"

[BeenRetired] TSMC quarterly chipmaking tool requirement ~1.9X their projection. The world's...

BeenRetired — 9/4/2026 11:18:48 AM

TSMC quarterly chipmaking tool requirement ~1.9X their projection.

The world's largest chipmaker just delivered the clearest real-time signal of how violently AI is reshaping semiconductor manufacturing: TSMC's quarterly requirement for chipmaking tools has climbed to nearly 1.9 times what the company projected at the end of 2025 — and it still cannot keep up with customers. Tool demand nearly doubled in one of the steepest surges in the industry's history.

What Hou described is not a demand surge that will ease with a few more fabs and a bit more capital. It reflects a structural mismatch between what the AI industry needs and the physical world's ability to produce it — one whose most binding constraint turns out not to be financing or technology, but the people who build cleanrooms.

TSMC's Q2 2026 results captured the financial scale of the moment: $40.2 billion in revenue, up roughly 34 percent year-over-year, with a gross margin of 67.7 percent. In response to the demand environment, TSMC raised its full-year capital expenditure guidance to $60 to $64 billion, up from an earlier range of $52 to $56 billion — a revision of roughly 90 percent above the estimate TSMC had posted at the end of 2025. TSMC's revised 2026 capex guidance makes it the largest single-year capex guidance revision in TSMC's modern history. For 2026 as a whole, TSMC now expects revenue growth of slightly more than 40 percent in US dollar terms, upgraded twice from the original near-30 percent forecast set in January.

CEO C.C. Wei has said he expects AI-driven semiconductor demand to remain structurally strong all the way through 2029 and 2030. He also acknowledged — at TSMC's annual shareholder meeting in Hsinchu in June — that the company cannot satisfy every customer. Wei told Hsinchu shareholders: "It will be a long time before we can meet customer demand." He added that ensuring TSMC does not become a bottleneck for the global AI supply chain is the company's core operational challenge.

TSMC Equipment Demand Doubled, But Fab Construction Workers Are Running Out

[BeenRetired] 576GB HBM3E supported: Threadripper Halo Station: AMD's First Personal Super...

BeenRetired — 9/4/2026 11:00:10 AM

576GB HBM3E supported:
Threadripper Halo Station: AMD's First Personal Supercomputer
The more significant announcement for enterprise and research users is the Threadripper Halo Station, which AMD revealed publicly for the first time at IFA 2026. The system is designed around a different architecture than the Ryzen AI Max Pro 400: instead of a single unified-memory SoC, it pairs a 96-core Threadripper PRO CPU with two AMD Instinct MI350P PCIe accelerator cards, with a hardware path to four, according to the IFA keynote transcript.

Each MI350P card carries 144GB of HBM3E memory running at 4TB per second — a fundamentally different class of memory than LPDDR5X, with bandwidth more than 14 times higher per card, as confirmed by Tom's Hardware's MI350P announcement coverage. In the two-card configuration announced at IFA, the Threadripper Halo Station provides 288GB of HBM3E. With the full four-card expansion, that ceiling rises to 576GB of HBM3E — enough, at aggressive quantization, to hold a trillion-parameter-class model in accelerator memory. The system is liquid cooled and also supports up to 2 terabytes of conventional system RAM for the CPU. AMD says it can run AI models exceeding 1 trillion parameters.

This is categorically different from consumer AI PC platforms. HBM3E's bandwidth advantage over LPDDR5X is not incremental: at 4TB per second per card versus 273GB per second for the entire Kraken Halo platform, each MI350P provides approximately 14.6 times the memory bandwidth of the full Kraken Halo system. For inference on models large enough to require the Threadripper Halo Station, that bandwidth gap determines how many tokens per second are achievable. Pricing, availability, and configurations for the Threadripper Halo Station were not announced at the keynote.

Frequently Asked Questions
What is the Threadripper Halo Station, and when does it go on sale?
The Threadripper Halo Station is a liquid-cooled workstation AMD announced for the first time at IFA 2026 on September 4, 2026. It pairs a 96-core Threadripper PRO CPU with two AMD Instinct MI350P accelerator cards, each carrying 144GB of HBM3E memory at 4TB per second — totaling 288GB of accelerator memory in the base configuration, with expansion to four cards (576GB) supported. AMD says the system can run AI models with more than 1 trillion parameters. Pricing, availability, and the full system specification have not been announced, according to the IFA 2026 keynote transcript.

Why can't I just add more VRAM to a discrete GPU system to get the same result as unified memory?
The 192GB unified memory in Kraken Halo is not equivalent to 192GB of discrete GPU VRAM, and the difference is structural. In a discrete GPU system, the GPU's VRAM and the CPU's system RAM are physically separate pools connected by a PCIe bus. Data must be explicitly copied from system RAM into VRAM before the GPU can use it. More critically, if a model's weights exceed VRAM capacity, it cannot run on that GPU — period. The largest commercially available single discrete GPU (NVIDIA H200 NVL) carries 141GB of HBM3E memory, as itechguides' unified memory explainer details. The Ryzen AI Max Pro 400 at 192GB, with up to 160GB allocatable as GPU memory, reaches parameter scales no single discrete GPU can address, as confirmed by Tweaktown's Ryzen AI Max coverage.

What OEM systems are available on Kraken Halo, and what do they cost?
As of the IFA 2026 keynote, two commercial OEM systems were confirmed: the Lenovo ThinkCentre X compact desktop and the HP ZBook codenamed Sundance, a creative-professional laptop with 190GB of unified memory. AMD's own second-generation Ryzen AI Halo developer box — an updated version of the $3,999 (USD) first-generation system — was also shown; updated pricing has not been announced. Additional systems from ASUS were previously indicated for Q3 2026 availability but were not confirmed at the keynote.

AMD used the opening keynote of IFA 2026 this morning — the first time in the show's 102-year history that a silicon company has held that slot — to announce two hardware platforms that move the boundary of what a local AI system can do. The more anticipated of the two, the Ryzen AI Max Pro 400 platform (codenamed Kraken Halo), arrived with confirmed commercial systems from Lenovo and HP. The less anticipated was the headline: the Threadripper Halo Station, a liquid-cooled workstation announced for the first time at IFA that AMD says can run AI models with more than 1 trillion parameters locally, without a cloud connection.

AMD launches Threadripper Halo Station at IFA, targets trillion-parameter local AI

[BeenRetired] ARM CPUs have 45% of Data Center revenue. Tom's Hardware reports that Arm-based...

BeenRetired — 9/4/2026 10:39:02 AM

ARM CPUs have 45% of Data Center revenue.

Tom's Hardware reports that Arm-based server CPUs now account for 45% of the data center market's revenue. Arm-based systems are experiencing solid demand due to their higher energy efficiency and performance for inference and agentic AI workloads. This explains why Arm-based server CPUs are anticipated to capture 90% of the server CPU market by 2029, according to Counterpoint Research.

Nvidia just delivered a massive warning to AMD and Intel stock investors

Key takeaways

Revenue Growth: Nvidia reported 106% YoY revenue increase to $96.2B, driven by data center demand from hyperscalers, AI labs, and neocloud companies.
Server CPU Expansion: The new Vera CPU, based on Arm v9.2-A architecture, targets major hyperscalers like AWS, OCI, and SpaceXAI, with projected $20B revenue in 2026 and rapid growth expected through 2028.
Market Impact: Nvidia’s fast-growing server CPU business threatens Intel and AMD, as Arm-based CPUs gain traction for energy efficiency and AI workloads, potentially capturing 90% of the market by 2029.

PS
Who isn't making Leading-Edge Logic?
Rolling MoAPS bonanza JUST started.
:-)

[BeenRetired] N2P SM8975E = Bullet train high ballin' to bit intensity land. :-)

BeenRetired — 9/3/2026 7:04:18 PM

[BeenRetired] Copilot: "This is Qualcomm’s 'all-in' node transition"

BeenRetired — 9/3/2026 7:00:28 PM

[BeenRetired] Copilot: "every major block is upgraded simultaneously"

BeenRetired — 9/3/2026 6:58:59 PM

[BeenRetired] Copilot: "N2P SM8975 enhanced is “stuffed to the gills.” Yes — your intuition ...

BeenRetired — 9/3/2026 6:57:12 PM

Copilot: "N2P SM8975 enhanced is “stuffed to the gills.”

Yes — your intuition is exactly right. The SM8975 enhanced (TSMC N2P) platform is shaping up to be the most feature-dense mobile SoC ever shipped, and the SDR765 ? N6RF migration is one of several signals that Qualcomm is stacking the entire 2026–2027 flagship platform with advanced nodes, advanced RF, and next-gen memory + AI subsystems.

Let me break down the architecture cleanly and show why N2P SM8975 enhanced is “stuffed to the gills.”

1. SDR765 moving from Samsung 14RF ? TSMC N6RF is a big deal
This shift matters because:

Samsung 14RF ? TSMC N6RF

Much lower leakage
Higher RF linearity
Better coexistence with mmWave + satellite bands
Higher QAM stability (1024-QAM uplink/downlink)
Better integration with N3/N2 baseband logic

And yes — Apple’s C1 modem uses the same N6RF node, so Qualcomm is aligning with the highest-performing RF silicon available.

This is the RF foundation for the SM8975 enhanced platform.

2. SM8975 enhanced (TSMC N2P) is absolutely loaded with advanced features
Here’s the operator-grade breakdown of what’s inside or strongly signaled:

A. LPDDR6

Qualcomm already confirmed LPDDR6 support in SM8750 (N3E).
SM8975 enhanced on N2P will support:
- LPDDR6 10,000–12,800 MT/s
- LPDDR6X variants for ultra-high bandwidth
This is essential for:
- 1–3B parameter on-device AI models
- 4K/5K AMOLED pipelines
- High-refresh gaming workloads

LPDDR6 is a lock.

B. X105 modem
The X105 modem is expected to be:

N3E or N2P logic
Paired with SDR765 on N6RF
Supporting:
- 1024-QAM UL/DL
- NTN satellite bands (n253/n255/n256)
- 4×4 MIMO downlink
- 2×2 uplink
- Massive CA aggregation
- 7-carrier downlink CA
- 3-carrier uplink CA

This is the most advanced RF + modem pairing Qualcomm has ever shipped.

C. Next-gen AI processor (Hexagon Gen 9 or Gen 10)
Qualcomm’s AI roadmap shows:

2×–3× performance per watt jump from N3E ? N2P
Dedicated blocks for:
- multimodal fusion
- camera semantic segmentation
- on-device LLMs
- RAG pipelines
- vector search
- low-latency AR overlays

This is where N2P’s BSPDN and nanosheet drive current matter.

D. 2nm GPU (Adreno Gen 10)
Expect:

Ray tracing improvements
Higher sustained clocks due to BSPDN
Better thermal stability
Higher FP16/FP8 throughput for AI graphics workloads

E. Advanced ISP + camera pipelines
With 2nm efficiency:

4K/5K AMOLED displays
200–300 MP sensors
8K HDR video
Real-time semantic segmentation
Multi-frame fusion
Night mode with AI denoising

These pipelines are extremely power-hungry — N2P is required.

F. BSPDN (Backside Power Delivery)
TSMC N2P introduces:

10–20% higher frequency headroom
Lower IR drop
Better thermal distribution
Higher sustained performance

This is why SM8975 enhanced is expected to outperform Apple A20 in sustained workloads.

3. Why SM8975 enhanced is “stuffed to the gills”
Because Qualcomm is aligning every subsystem with:

TSMC N2P logic
TSMC N6RF RF
LPDDR6 memory
X105 modem
Next-gen AI + GPU blocks
BSPDN power delivery
Pixel-dense AMOLED pipelines
Satellite NTN bands
High-refresh gaming

This is the first Qualcomm platform where every major block is upgraded simultaneously.

Bottom Line (Operator-grade)
Yes — SM8975 enhanced on TSMC N2P is absolutely packed with advanced features. The SDR765-> N6RF migration is just one piece of a much larger architecture shift.

The 2H26–2027 Qualcomm flagship will be:

the first full 2nm + LPDDR6 + BSPDN mobile platform
with the most advanced RF system Qualcomm has ever shipped
and the most AI-dense mobile processor on the market

This is Qualcomm’s “all-in” node transition.

[BeenRetired] But...wait...there's more: Wi-Fi 8 & UFS 5.0. How Does Wi-Fi 8 Actually...

BeenRetired — 9/3/2026 6:49:20 PM

But...wait...there's more: Wi-Fi 8 & UFS 5.0.

How Does Wi-Fi 8 Actually Work?
Both wireless companion chips — the WCN8841 and WCN8851, part of the FastConnect 8800 family — support Wi-Fi 8 in a 2×2 MIMO configuration at 300 MHz. Wi-Fi 8 is based on the IEEE 802.11bn amendment, which targets Ultra High Reliability (UHR) rather than simply higher peak throughput: the standard specifies at least a 25 percent reduction in 95th-percentile latency, a 25 percent improvement in throughput under real-world range conditions, and a 25 percent reduction in packet loss during access-point transitions. That means Wi-Fi 8 is designed to make wireless connections behave more like wired ones in congested environments — an advantage for cloud gaming, XR applications, and real-time video collaboration.

Qualcomm is reportedly offering a binned SM8975 variant — with lower CPU and GPU clock ceilings — at a reduced price to partners who want the silicon tier without paying for maximum clocks, mirroring the approach Apple uses with its A-series Pro and standard die differentiations. Some manufacturers may also trim camera hardware to offset SM8975's higher cost. Counterpoint Research has noted that LPDDR6 plus UFS 5.0 memory configuration costs can exceed the SoC cost itself at current memory prices — a Bill of Materials configuration that did not exist at this price tier in any prior Snapdragon generation.

[BeenRetired] 6nm SDR765, sub-6 GHz-only companion transceiver, moves manufacturing from Samsu...

BeenRetired — 9/3/2026 6:25:58 PM

6nm SDR765, sub-6 GHz-only companion transceiver, moves manufacturing from Samsung's 14nm RF process to TSMC's N6RF node — the same RF node used in Apple's C1 modem.

PS
What I keep reading.
Vicious Fone competition drives yearly Shrink n Stack n Package.
Moore on steroids.
Adds Cuz More than Moore.

PS
Wearables & Mobile just as important for SVG/Cymer/Brion/HMI/Mapper/Berliner Glas/ASML/et al tool fleet as AI.

PSS
EUV bigger deal than Dot Com.

[BeenRetired] ~$33K 2nm wafer: Bigger die for even more circuits. LPDDR6 on board SM8975 ...

BeenRetired — 9/3/2026 6:03:44 PM

~$33K 2nm wafer: Bigger die for even more circuits. LPDDR6 on board SM8975

Notebookcheck's team calibrated the SM8975's physical die against Qualcomm's official package dimensions of 21.2 mm × 14 mm (0.835 in × 0.551 in) and arrived at a die measurement of approximately 12.6 mm × 10.67 mm (0.496 in × 0.420 in), or roughly 134 square millimeters. That is larger than the Snapdragon 8 Elite Gen 5's confirmed die area of 126.2 mm², even though the SM8975 moves to a more advanced manufacturing process.

The explanation is architectural complexity. The additional Matrix ALU blocks, a larger last-level cache, and a revised GPU take up area that the process-node shrink alone cannot recover. The SM8975 reportedly uses TSMC's N2P process — an enhanced 2nm-class node that employs nanosheet (gate-all-around) transistors, one step beyond the 3nm FinFET process used in the Snapdragon 8 Elite Gen 5. N2P's wafer cost has been modeled at roughly $33,000 per wafer, compared to approximately $20,000 for a 3nm wafer — a driver of the higher OEM pricing.

For competitive context, the SM8975 at 134 mm² remains smaller than MediaTek's Dimensity 9500 at approximately 140 mm², suggesting that Qualcomm's 2nm move is delivering real density gains even with the added compute blocks. The Apple A20 Pro, which is expected to power iPhone 18 Pro models later this year, uses the baseline N2 node rather than the enhanced N2P variant — meaning the SM8975 sits on a slightly more advanced process flavor than its Apple rival.

That placement matters for frame generation specifically. A standalone NPU and the GPU occupy separate memory domains; running AI inference on an NPU while the GPU renders means data must travel across the chip's main interconnect bus. By placing the Matrix ALUs inside the shader processor, the SM8975 keeps the AI inference needed for upscaling and frame generation inside the same fast GMEM that the GPU is already using for rendering — eliminating the latency of that external bus trip. That is what makes real-time frame generation on a mobile phone GPU feasible in a way that NPU-to-GPU coordination would make much harder.

LPDDR6: Android Gets a Memory First
One of the SM8975's most consequential specifications is memory support. The chip will mark the first appearance of LPDDR6 RAM on an Android platform. OEMs may configure the SM8975 with either quad-channel 24-bit LPDDR6 or quad-channel 16-bit LPDDR5X, paired with 8 MB of last-level cache. The standard SM8950 is limited to LPDDR5X only.

LPDDR6 was standardized by JEDEC as JESD209-6 in July 2025 and uses a dual-subchannel architecture with 12 data lines per subchannel. Peak data rates reach up to 14.4 Gbps per pin, compared to 10.67 Gbps for LPDDR5X — a bandwidth improvement of roughly 35 percent at the high end. Samsung demonstrated working LPDDR6 silicon at CES 2026, reporting approximately 21 percent better power efficiency than the previous generation. Apple is reportedly sticking with LPDDR5X for the iPhone 18 series, leaving Android as LPDDR6's first mobile testing ground.

The AI angle is significant. Large language models running locally on a phone are increasingly limited by memory bandwidth, not by compute alone. A model that fits in RAM but cannot stream weights to the processor fast enough stalls inference in ways the user notices as sluggish response time. LPDDR6's bandwidth increase translates directly to faster on-device AI responses and higher-quality real-time image generation.

The cost problem is equally real. LPDDR6 currently carries a roughly 20 percent cost premium over LPDDR5X. Combined with the DRAM and NAND supply crisis that has already pushed memory component costs up 40 to 50 percent quarter-over-quarter in late 2025, that premium lands on top of an already elevated baseline. Counterpoint Research has stated directly that "higher retail prices are unavoidable in 2026 as rising costs will be passed to consumers," with the firm estimating a $150 to $200 increase per premium device. OEMs that choose LPDDR5X configurations to keep costs down will sacrifice the bandwidth advantage — and consequently some of the AI Frame Fusion pipeline performance.

Storage steps up to UFS 5.0 on the Pro, with two high-bandwidth lanes, versus UFS 4.0 or UFS 5.0 (single lane) on the standard variant depending on OEM configuration.

Modem and RF: Symmetric Upload Arrives for the First Time
The SM8975 pairs with Qualcomm's new X105 modem, its first appearance on a shipping Snapdragon platform. Both the SM8975 and the standard SM8950 reportedly use the same RF front end, which is not backward-compatible with prior-generation modems — meaning the standard Gen 6 will ship with some configuration of the X105 as well, rather than reusing prior-generation silicon.

The more technically significant RF story is the SDR885 transceiver. It is, per the leaked documentation Notebookcheck reviewed, Qualcomm's first sub-6 GHz transceiver to support 4×4 MIMO on both uplink and downlink simultaneously. In prior generations, uplink MIMO was limited — 2×2 uplink against 4×4 downlink was typical — meaning upload throughput was structurally capped below download speeds regardless of network conditions. The SDR885 removes that asymmetry with a 20-transmit-port configuration (arranged 7+7+3+3) and 16 primary plus 16 diversity receive-input paths, under 3GPP Release 18.

The SDR765, the sub-6 GHz-only companion transceiver, moves manufacturing from Samsung's 14nm RF process to TSMC's N6RF node — the same RF node used in Apple's C1 modem-RF system. It supports 2×2 MIMO uplink and 4×4 downlink, 1024-QAM modulation, and the n253, n255, and n256 satellite bands.

How Does Wi-Fi 8 Actually Work?
Both wireless companion chips — the WCN8841 and WCN8851, part of the FastConnect 8800 family — support Wi-Fi 8 in a 2×2 MIMO configuration at 300 MHz. Wi-Fi 8 is based on the IEEE 802.11bn amendment, which targets Ultra High Reliability (UHR) rather than simply higher peak throughput: the standard specifies at least a 25 percent reduction in 95th-percentile latency, a 25 percent improvement in throughput under real-world range conditions, and a 25 percent reduction in packet loss during access-point transitions. That means Wi-Fi 8 is designed to make wireless connections behave more like wired ones in congested environments — an advantage for cloud gaming, XR applications, and real-time video collaboration.

One important caveat: the 802.11bn standard has not yet been ratified and is not expected to reach final ratification until approximately 2028. Devices shipping in 2026 and early 2027, including those based on the FastConnect 8800, will operate on draft specifications. If the ratified standard diverges from the draft in ways that affect core operating parameters, early adopters could face compatibility limitations with certified Wi-Fi 8 access points. That scenario has precedent — Wi-Fi 6E and Wi-Fi 7 both saw interoperability issues in early deployments.

The two FastConnect chips differ by tier. The WCN8841 supports Bluetooth 6.0 and 2×2 MIMO at 300 MHz. The WCN8851 steps up with Bluetooth 7.0, a second Wi-Fi radio path capable of 2×4 or 4×4 MIMO at 320 MHz, Bluetooth 7.0 extended to the 5 GHz and 6 GHz bands, and ultra-wideband (UWB) for precision spatial positioning.

Which Phones Will Carry the SM8975 — and When?
Qualcomm's Snapdragon Summit 2026 is officially confirmed for September 22 to 24 in Maui, Hawaii. That is where the SM8975 is expected to be formally unveiled. Xiaomi is widely expected to be among the first out of the gate, potentially announcing a Gen 6 Pro-powered device alongside Qualcomm's keynote.

The SM8975 is expected to be reserved for a narrower tier of devices than the standard SM8950 — Ultra-branded phones, select foldables, and a small number of premium gaming devices. The Samsung Galaxy S27 Ultra is among the most-cited candidates, along with the Xiaomi 18 Ultra, Oppo Find X10 Ultra, and OnePlus 16. Most commercial handsets using the Gen 6 Pro are expected to appear in the second half of 2026 and through early 2027.

Qualcomm is reportedly offering a binned SM8975 variant — with lower CPU and GPU clock ceilings — at a reduced price to partners who want the silicon tier without paying for maximum clocks, mirroring the approach Apple uses with its A-series Pro and standard die differentiations. Some manufacturers may also trim camera hardware to offset SM8975's higher cost. Counterpoint Research has noted that LPDDR6 plus UFS 5.0 memory configuration costs can exceed the SoC cost itself at current memory prices — a Bill of Materials configuration that did not exist at this price tier in any prior Snapdragon generation.

Spec Breakdown: Gen 6 Pro vs. Gen 6

FeatureSnapdragon 8 Elite Gen 6 Pro (SM8975)Snapdragon 8 Elite Gen 6 (SM8950)

Process	TSMC N2P (2nm-class, enhanced)	TSMC N2 (2nm-class, baseline)
Die Size	~134 mm² (~0.208 in²)	Not confirmed
CPU	2+3+3 Oryon	2+3+3 Oryon
GPU	Adreno 850, 18 MB GMEM	Adreno 845, 12 MB GMEM
Matrix ALUs	Yes (two blocks, shader-integrated)	No
AI Frame Fusion	Yes	No
RAM	LPDDR6 or LPDDR5X (OEM choice)	LPDDR5X only
Storage	UFS 5.0	UFS 4.0 or UFS 5.0 (single lane)
L2 Cache (shared)	16 MB	16 MB
Last-Level Cache	8 MB	6 MB
Modem	X105 (full config)	X105 (reduced config)
Wi-Fi	Wi-Fi 8, FastConnect 8800	Wi-Fi 8, FastConnect 8800
Bluetooth	Up to 7.0 (WCN8851)	Up to 7.0 (WCN8851)
UWB	Yes (WCN8851 config)	Yes (WCN8851 config)
Expected launch	Snapdragon Summit, Sept. 22–24, 2026	Snapdragon Summit, Sept. 22–24, 2026

All specifications are pre-announcement leaks; Qualcomm has not confirmed any SM8975 details.

Should You Wait for a Gen 6 Pro Phone?
The decision splits cleanly along use case lines. If you are a high-fps mobile gamer, the combination of AI Frame Fusion and LPDDR6 bandwidth represents a genuine generational shift — better sustained frame rates, AI-assisted upscaling, and the memory bandwidth to run on-device AI models without cloud offload. If you primarily use your phone for productivity, photography, and communication, the standard Gen 6 or even a current Snapdragon 8 Elite Gen 5 device will cover most of your needs at a meaningfully lower price.

What exactly is AI Frame Fusion, and how is it different from what current Android phones can do?
AI Frame Fusion uses two Matrix ALU blocks embedded inside the Adreno 850's shader processor — the same computing blocks that handle rendering — to run neural network inference on a game's motion and depth data. The super-resolution mode reconstructs high-resolution frames from lower-resolution rendering output; the frame-generation mode synthesizes new frames between rendered frames to increase perceived frame rate. Current Android flagships rely on the Snapdragon Game Super Resolution (SGSR) system, which uses fixed-function rather than Matrix ALU-accelerated upscaling and does not include frame interpolation. No Android phone currently supports GPU-shader-integrated AI frame generation.

What does symmetric 4×4 MIMO uplink mean for everyday connectivity?In prior Snapdragon generations, the modem supported 4×4 MIMO for downloads but typically only 2×2 MIMO for uploads, meaning upload speeds were structurally slower than download speeds regardless of the network. The SDR885 transceiver in the SM8975 generation introduces 4×4 MIMO on both uplink and downlink — the first time this configuration has appeared in a Snapdragon platform. In practical terms, this means the theoretical ceiling for mobile upload speeds will be meaningfully higher on Gen 6 Pro devices, which matters for large file uploads, real-time video streaming, and cloud-sync-heavy workflows on 5G networks.

[BeenRetired] Qualcomm Adreno Neural Fusion puts AI inside mobile GPU: Unity and Unreal alread...

BeenRetired — 9/3/2026 5:48:56 PM

Qualcomm Adreno Neural Fusion puts AI inside mobile GPU: Unity and Unreal already onboard

Tech Times

Qualcomm Adreno Neural Fusion puts AI inside mobile GPU: Unity and Unreal already onboard
Story by Edward Northmore
Sep 03 • 10 min read • Updated 59m ago

Key takeaways

AI-Enhanced Rendering: The Adreno Neural Fusion GPU embeds Matrix Cores inside each GPU slice, enabling super-resolution and frame generation directly on the GPU without extra coding.
Efficiency Boost: This architecture reduces power consumption by up to 40%, keeps AI inference local to the GPU’s 18MB High Performance Memory, and improves overall GPU efficiency by 12%.
Unified Matrix Compute: Every core engine — GPU, CPU, and Hexagon NPU — now supports matrix operations for AI, allowing dynamic routing of tasks for low-latency, frame-by-frame AI processing.

Qualcomm has officially named and detailed the GPU architecture powering its next flagship Snapdragon platform — and the design draws a sharp architectural line between hardware-accelerated AI rendering and every mobile GPU that came before it. The company disclosed the Adreno Neural Fusion GPU on September 2, 2026, revealing that dedicated AI compute units called Matrix Cores now sit inside each of the GPU's three processing slices, and that both Unity and Unreal Engine already have native integration built in — meaning developers can enable AI-enhanced rendering without writing a single line of custom code.

The practical consequence for Android flagship buyers is this: the games they already play — or will download — on a next-generation Snapdragon device should run longer and look sharper on the same battery budget, through upscaling and frame generation that runs entirely inside the graphics chip rather than bouncing data across the chip to a separate AI processor.

Why Putting AI Inside the GPU Slice Changes the Equation
The defining architectural fact of Adreno Neural Fusion is not merely that the new GPU supports AI workloads — the existing Hexagon NPU in every Snapdragon chip already handles AI inference. What is new is where the AI runs: inside each of the three GPU slices, co-located with the 18MB of Adreno High Performance Memory (HPM) that the GPU uses for its tile-based rendering pipeline. Qualcomm's official blog describes the HPM as providing "large, low-latency memory directly to the GPU, allowing tile-based rendering, frame buffers, and compute workloads to remain local to the graphics subsystem."

Mobile GPUs process frames using tile-based deferred rendering — they subdivide the framebuffer into small tiles and complete all the processing for each tile in fast on-chip memory before writing the finished result to main system RAM. The 18MB HPM is that fast on-chip memory. Keeping AI inference data inside the same 18MB pool means the super-resolution and frame generation algorithms read from and write to the same memory the GPU is already using, at the same speed. The Snapdragon Game Super Resolution documentation on GitHub confirms that SGSR v2 already used temporal data to improve upscaling quality — Neural Fusion takes the next architectural step by putting that inference work on dedicated hardware.

Prior approaches — including Qualcomm's own Snapdragon Game Super Resolution — ran upscaling algorithms on the GPU's general shader cores, and more complex AI tasks were routed to the Hexagon NPU. The Futurum Group's analysis of early GSR describes the original approach: a single-pass spatial technique optimized for Adreno GPUs that achieved power savings at the cost of reconstruction quality. Sending data to the NPU required writing to shared memory or DRAM, crossing the chip's system interconnect bus, waiting for the NPU to run inference, and reading the results back — each step adding latency and energy overhead. The Matrix Cores eliminate those bus crossings by keeping AI inference physically adjacent to where frames are rendered.

Qualcomm claims this architectural approach delivers up to 40% lower power compared to the prior-generation Snapdragon Game Super Resolution system — a self-reported figure against Qualcomm's own prior solution, pending independent third-party validation after Snapdragon Summit. A separate 12% overall GPU efficiency improvement, generation over generation, applies to the broader GPU architecture regardless of Neural Fusion being active.

The Matrix Cores run at 1.45GHz — the same clock speed as the GPU slices they are embedded in — up from the 1.2GHz of the Adreno 840 GPU in the current Snapdragon 8 Elite Gen 5, according to AndroidHeadlines' coverage of the disclosure.

Completing Qualcomm's Matrix Compute Trifecta
The Adreno Matrix Cores are not an isolated addition. They complete what Qualcomm now describes as a platform-wide matrix acceleration strategy spanning all three of its core compute engines, as documented in XenoSpectrum's Neural Fusion analysis.

The Hexagon NPU has carried dedicated matrix compute units for multiple Snapdragon generations — it has long been the primary home for large AI inference workloads running in the background. The Oryon CPU, previewed on August 25, 2026, added Scalable Matrix Extension support, embedding matrix acceleration into the CPU cores for AI tasks that run in parallel with foreground applications. Now, with Matrix Cores inside the Adreno GPU slices, every major processing engine on the next flagship Snapdragon platform can accelerate General Matrix Multiply operations — the mathematical primitive underlying virtually all neural network inference.

The practical implication is workload routing: the platform can dynamically assign AI inference tasks to whichever engine is best suited — the NPU for sustained background models, the CPU for foreground tasks, and the GPU Matrix Cores for AI operations that need to happen inside the graphics pipeline frame by frame.

Anshel Sag, a principal analyst at Moor Insights & Strategy, noted in a Moor Insights analysis published September 2 that the Adreno Matrix Core architecture is "similar to what Apple did with Apple Silicon's GPU" — a reference to Apple's integration of GPU-embedded matrix compute units across its A-series and M-series silicon. He characterized the GPU Matrix Cores as providing meaningful complementary AI compute horsepower alongside the NPU — not replacing it, but routing an entire category of latency-sensitive AI work to silicon that was previously unavailable for it.

Adreno Neural Fusion bundles two distinct AI rendering capabilities under one pipeline. The first is AI super-resolution: the game renders internally at a lower resolution — reducing GPU workload and power draw — while the Matrix Cores run a neural network that reconstructs the full output resolution with sharp detail. Earlier mobile upscalers, including Qualcomm's GSR v1, used spatial algorithms without motion data; GSR v2 added temporal data but ran on conventional shader cores. Neural Fusion runs on dedicated hardware, allowing more sophisticated network architectures at lower power cost. The GSR GitHub repository documents this lineage from single-pass spatial upscaling to temporal reconstruction.

The second capability is frame generation: the Matrix Cores synthesize entirely new intermediate frames between natively rendered frames using motion vectors and optical flow data. Rather than rendering every displayed frame from scratch, the GPU renders fewer frames and uses AI to construct the frames in between — maintaining smooth visual output at lower GPU utilization. Qualcomm's official description positions this as delivering "stable frame rates and improved efficiency through AI-enhanced rendering built directly into the Snapdragon graphics pipeline."

A note that every major PC implementation of frame generation carries applies here as well: synthesized frames are computed after the rendered frames they sit between, which adds display latency compared to native rendering at the same frame count. PC frame generation latency research — including Hardware Unboxed's testing and Digital Foundry's analysis — documents latency additions of 10 to 30 milliseconds at common frame-rate targets, depending on configuration. For visually driven, single-player, and casual gaming experiences, this latency is imperceptible. For competitive mobile gaming requiring reflex-based input, frame generation is typically not the recommended mode — and Qualcomm's AI rendering suite does not change that underlying tradeoff. The suite's 40% power savings claim applies specifically to upscaling workloads; competitive-gaming players who prioritize touch-to-display latency should monitor how developers configure frame generation in titles they play.

Unity and Unreal Engine Integration: Why "Already Onboard" Matters
Hardware capabilities and consumer games exist on opposite ends of an adoption pipeline. A GPU that can do frame generation in a first-party demo is interesting engineering. A GPU whose frame generation runs in the game development tools that studios already use is what players actually experience.

Qualcomm confirmed that both Unity and Unreal Engine — the two platforms powering the substantial majority of mobile games globally — have already integrated Neural Fusion natively. Studios building on either engine can enable super-resolution and frame generation within their existing development workflows without writing custom rendering code or waiting for engine-level support to arrive. The integration is available at ship time, not on a future roadmap, as HotHardware confirmed in its coverage of the announcement.

This is the crossover mechanism. NVIDIA DLSS offers a useful parallel: the technology launched in 2018 requiring per-title custom integration. Adoption was slow. When Unreal Engine built native DLSS support into its plugin architecture, the number of supported titles expanded rapidly without requiring per-studio engineering investment. Qualcomm has apparently applied that lesson — securing engine-level integration before the chip is in consumer devices, so the features are available to any developer who targets the platform from launch.

What Does Adreno Neural Fusion Do Differently Than Older Snapdragon GSR?
The Snapdragon Game Super Resolution system that Neural Fusion supersedes went through two generations: GSR v1 was a single-pass spatial upscaler using fixed-function sharpening algorithms — effectively a GPU-side equivalent to AMD FSR 1.0, efficient but limited in output quality. The Snapdragon GSR GitHub repository documents both generations: GSR v2 added temporal data (motion vectors and frame history), improving stability but still relying on general shader cores rather than dedicated hardware.

Neural Fusion moves to hardware-accelerated neural network inference with Matrix Cores — the architectural leap that separates DLSS from FSR on the PC side. Benchmark comparisons of DLSS and FSR show DLSS consistently producing cleaner output than FSR's algorithmic approach at equivalent frame rates, a gap explained by DLSS running on NVIDIA's Tensor Cores (dedicated GEMM accelerators in RTX GPUs). Neural Fusion is Qualcomm's implementation of the same fundamental principle: dedicated matrix compute hardware accelerating neural upscaling within the graphics pipeline, producing output with fewer ghosting and shimmering artifacts than temporal-only predecessors.

A Pre-Announcement Architecture Preview
Qualcomm has not officially named the Snapdragon platform that will carry this GPU. Neither the SKU designation nor the manufacturing process node has been publicly confirmed. What Qualcomm has confirmed is that the chip's architecture preview has arrived in two distinct disclosures — the Oryon CPU 5GHz and FlexCache cache architecture on August 25, followed by the Adreno Neural Fusion GPU on September 2 — with the Hexagon NPU details still to come.

The complete platform is expected to be unveiled at Snapdragon Summit 2026, which will take place September 22 to 24 in Maui, Hawaii. That event is expected to bring official benchmark results, confirmed specifications, and live demonstrations of Neural Fusion running in supported titles.

Publishing GPU microarchitecture details before the host SoC has been officially named is an unusual cadence — it signals that Qualcomm considers the graphics story significant enough to carry its own pre-Summit spotlight, separate from the full chip launch.

What This Means for Android Flagships
Premium Android handsets powered by the next Snapdragon platform should offer meaningful gains in sustained gaming — higher visual quality at lower power draw than current-generation Snapdragon devices — and those gains should appear in existing games built on Unity or Unreal Engine rather than only in titles developed specifically for the new hardware. Brands including Samsung, Xiaomi, OnePlus, and others routinely power their premium Android lineups with Qualcomm's flagship silicon.

Whether Qualcomm's 40% power savings claim holds up under independent testing remains to be established — that evidence will arrive after the chip ships in consumer devices. The comparison baseline ("previous solutions") is Qualcomm's own prior GSR system, and real-world results depend on workload, game engine configuration, target resolution, and thermal conditions. What is not in question is the architectural direction: GPU-embedded AI acceleration, on-chip memory adjacency, and engine-native developer tools are the mechanisms that convert a hardware announcement into a feature that players actually experience.

Frequently Asked Questions
What is Adreno Neural Fusion and how is it different from what Snapdragon GPUs could do before?
Adreno Neural Fusion is Qualcomm's new mobile GPU architecture featuring dedicated Matrix Core AI compute units embedded inside each of the GPU's three slices. Prior Snapdragon GPUs used either fixed-function spatial upscaling (GSR v1) or temporal upscaling on general shader cores (GSR v2). Neither used dedicated AI hardware inside the graphics pipeline. Neural Fusion's Matrix Cores run neural network inference on the same on-chip memory the GPU uses for rendering — producing cleaner super-resolution output with fewer artifacts and enabling frame generation for the first time without routing AI tasks across the chip to a separate NPU. Qualcomm's official Neural Fusion blog describes this as the first time Adreno has packed dedicated AI-processing cores inside the graphics pipeline itself.

Will Adreno Neural Fusion work in games I already play, or only in new games designed for the chip?Qualcomm confirmed that Unity and Unreal Engine already have native integration for the Neural Fusion stack, which means studios using either engine can enable the super-resolution and frame generation features within their existing development pipelines without custom code. Games that are actively maintained and built on these engines — the two most widely used mobile game development platforms — are the most likely candidates for Neural Fusion support, though each studio will need to enable and configure the feature. XenoSpectrum's Neural Fusion coverage confirms the Day 1 integration status for both engines. Games that are no longer in active development will not receive it.

Is frame generation good for competitive mobile gaming?
Frame generation produces visually smoother output by synthesizing frames between natively rendered frames, but it adds display latency — a tradeoff documented consistently in PC implementations of DLSS Frame Generation and similar technologies. Research on PC frame generation latency shows synthesized frames are computed after the rendered frames they follow, so the time from input to displayed image is higher than native rendering at the same frame count. For casual gaming, role-playing games, and narrative-driven experiences, this latency addition is not noticeable. For competitive mobile games where millisecond-level input response matters — battle royale shooters, fighting games — frame generation is not the recommended configuration. Qualcomm's 40% power savings claim applies primarily to super-resolution workloads; competitive players should evaluate how individual titles implement frame generation before assuming it is appropriate for their use case.

When will phones with Adreno Neural Fusion be available to buy?
Qualcomm has not named the Snapdragon platform carrying this GPU architecture or confirmed its release timeline. The chip is expected to be officially unveiled at Snapdragon Summit 2026, which is scheduled to take place September 22 to 24 in Maui, Hawaii. Commercial handsets based on the platform are widely anticipated to follow in the second half of 2026 and into early 2027, consistent with Qualcomm's typical flagship launch cadence.

[BeenRetired] "Huang made it clear that he wants to reinvent PC with RTX Spark"

BeenRetired — 9/3/2026 5:34:23 PM

[BeenRetired] Nvidia’s RTX Spark N1X drops this October: My price predictions for the potentia...

BeenRetired — 9/3/2026 5:33:14 PM

Nvidia’s RTX Spark N1X drops this October: My price predictions for the potential MacBook Pro killer

Tom's Guide

Nvidia’s RTX Spark N1X drops this October: My price predictions for the potential MacBook Pro killer
Story by Jason England
Sep 03 • 4 min read • Updated 3h ago

Key takeaways

Powerful Specs: Features Grace CPU (18-20 cores) + Blackwell RTX GPU (5,120–6,144 CUDA cores) with up to 128GB unified memory, delivering high-end productivity and gaming performance.
Versatile Form Factors: Available in laptops, 2-in-1 convertibles, and mini PCs, all with premium designs, OLED/mini LED displays, and solid I/O options.
Premium Pricing: Baseline models expected around $1,999–$2,499, while maxed-out configurations for AI and heavy workloads could reach $4,000–$5,000+, directly competing with MacBook Pro.

For years, creatives and gamers have had to deal with the two-device compromise: you buy an M-series MacBook Pro for the seamless productivity and all-day battery life, and keep the power-hungry Windows gaming rig at home.

I’ve tested RTX Spark a few times now, and I believe it’s the end of that compromise. And at IFA 2026, Team Green has confirmed that the RTX Spark N1X is coming this October.

Nvidia is aggressively targeting Apple’s throat. By shifting to the Arm-based Grace CPU paired with Blackwell graphics, as you’d see in its RTX 50-series GPUs, and massive pools of memory, Nvidia is finally bringing the Apple Silicon paradigm to Windows — without sacrificing PC gaming.

Impressive power in a 14mm chassisThis isn’t the first foray with Windows on Arm that we’ve seen. Qualcomm’s Snapdragon X2 Elite continues to deliver strong performance and power efficiency. But RTX Spark goes at things a different way by chucking a massive GPU at the silicon.

In my time testing, that leads to super-powered prosumer productivity performance (especially with the software integrations across Blender and Adobe’s creative suite), stellar gaming performance and enough fuel for Nvidia’s mission to “reinvent the PC” with local agentic AI. And for that power efficiency side of things, it manages to keep the same performance both on and off the charger!

Up until this point, we’d only known about the top-of-the-line N1X chip. Now we know about the baseline option (also called N1X…this could get a little confusing).

Obviously it’s worth noting that with the lower power consumption of a laptop, even though it does have a massive amount of cores, you won’t get the same level of performance as a desktop-class GPU. Just fun for comparison's sake, you know?

The form factorsWe already know about eight laptops launching with RTX Spark N1X. You can see where I rank them all in a tiered list I did a couple of months ago. Basically, to match the premium specs of that chip, you’re getting premium shells that tick all the boxes needed to take on a MacBook Pro — metallic bodies, gorgeous displays (OLED or mini LED), solid ergonomics and plenty of I/O.

There are also a couple of mini PCs from Asus and MSI launching with the chip inside, and here at IFA, we’re getting word on two new systems coming to the party in October too:

Lenovo Yoga 9n 2-in-1: Another convertible RTX Spark system has arrived to take on MSI’s Prestige Flip N16. The chassis is just 14mm thin.
Acer SFF RTX Spark: A small form factor desktop that would look pretty perfect under my living room TV as well as my desk.

So that’s the next advantage over the MacBook — variety of designs.

The friction point: Predicting the price
While Nvidia was eager to show off the specs, it was noticeably silent on the price. Well, I’m gonna do some bac-of-the-napkin math here to fill this gap and make a prediction. Based on components and the direct competition with Apple, it’s obvious that these machines are going to carry a heavy premium.

The baseline prediction: The lower-tier configuration (18-core CPU, 5,120 CUDA cores, 24GB RAM) will likely start around the $1,999 to $2,499 range — pricing it directly against the base MacBook Pro models.
The agentic premium: If you want that maxed out configuration with 128GB of unified memory to run massive local AI models, expect a jaw-dropping price tag. Given that a maxed-out MacBook Pro easily pushes past the $4,500 mark, an equivalent N1X will likely land in the $4,000 to $5,000+ range.

Bookmark this and remind me in the comments if I get this wrong!

The early verdict
Way back at Computex 2026, Nvidia CEO Jensen Huang made it clear that he wants to reinvent the PC with RTX Spark. This is all fair and good, but I believe the real showcase of N1X here is not the local AI computation. That part is impressive, but it’s still up for debate on whether people will actually use their computers in this way.

The real game-changer here (to me at least) is the fundamental architectural shift that bridges the gap between serious productivity and high-end gaming — complete with all-day battery life (providing it does match up to Nvidia’s claims of course).

It’s the MacBook Pro that actually has games to play on, and if everything plays out the way I’m anticipating (and there’s no nasty surprises on the performance front), then Apple is finally going to have genuine, uncompromised competition.

[BeenRetired] AVGO XPU demand curve far steeper than '23–'25 Bottom Line (Operator-grade)Anth...

BeenRetired — 9/3/2026 5:12:07 PM

AVGO XPU demand curve far steeper than '23–'25

Bottom Line (Operator-grade)

Anthropic is now Broadcom’s #1 growth engine, overtaking Google in 2027.
Google remains enormous, but its TPU demand curve is flatter than Anthropic’s.
OpenAI becomes #2, with >5 GW deployments by 2028.
Meta ramps steadily, reaching 3 GW by 2028.
Broadcom’s XPU business is entering a multi-customer, multi-gigawatt era, with demand curves far steeper than anything seen in 2023–2025.

[BeenRetired] Why Demand Still Outstripping Capacity Is the Story* Broadcom's disclosure that ...

BeenRetired — 9/3/2026 4:55:48 PM

Why Demand Still Outstripping Capacity Is the Story*
Broadcom's disclosure that customer demand exceeds its own $115 billion fiscal 2027 guidance is the fact that changes how to read the rest of the numbers. A $16.7 billion quarter and a $21.7 billion Q4 guide are extraordinary. But they are smaller than they could be if CoWoS capacity, HBM allocation, and data center power were unconstrained. The $230 billion fiscal 2028 target is not Broadcom's ceiling — it is the number that Tan believes the supply chain can deliver, with the acknowledged caveat that actual demand exceeds even that figure.

The practical implication for the technology industry is that AI infrastructure build-out is being paced not by customer appetite — which appears essentially unlimited — but by the speed at which TSMC can expand packaging lines, SK Hynix and Micron can produce HBM stacks, and utility operators can permit and commission the power substations needed to run data centers consuming gigawatts of electricity.

RBC has projected the total AI semiconductor market could exceed $550 billion by 2028, per RBC's AI semiconductor forecast. If Broadcom's $230 billion target holds, it would represent roughly 40% of that market — through a business model built not on selling chips to everyone, but on designing chips for six specific customers who are each individually building AI infrastructure at a scale the world has not previously attempted.

PS
My story, too!
Sticking with facts...not alternate facts in echo chamber.

[BeenRetired] 2nd-largest XPU Jalapeño in '27...due to NXE Productivity

BeenRetired — 9/3/2026 4:36:34 PM

[BeenRetired] 5 largest hyperscalers Alphabet, Microsoft, Amazon, Meta & Apple — collectively ...

BeenRetired — 9/3/2026 4:28:54 PM

5 largest hyperscalers Alphabet, Microsoft, Amazon, Meta & Apple — collectively increased capital expenditures ~ 80% in 2026 to more than $700 billion

PS
2nm Thingy bonkers...because NXE ramping quite nicely.
~$30K wafers too valuable to waste.
Just part of mega-prong tailwind mesh.
:-)

[BeenRetired] Broadcom AI revenue tripled to $16.7B as demand outstrips its own $230B roadmap ...

BeenRetired — 9/3/2026 4:19:58 PM

Broadcom AI revenue tripled to $16.7B as demand outstrips its own $230B roadmap

Tech Times

Broadcom AI revenue tripled to $16.7B as demand outstrips its own $230B roadmap
Story by Elijah Armfield
Sep 03 • 13 min read • Updated 2h ago

Key takeaways

Record Revenue & Growth: Q3 AI semiconductor revenue hit $16.7B, more than triple YoY, now accounting for 56% of total revenue. Total revenue reached $29.59B, with non-GAAP EPS $3.32 and free cash flow $13.7B.
Key Customers & Capacity: Anthropic is set to become the largest XPU customer in 2027, surpassing Google, with a capacity ramp from 1 GW (2026) ? 5 GW (2027) ? 10 GW (2028). OpenAI and Meta also expanding custom accelerator deployments.
Forward Outlook: Fiscal 2027 AI revenue projected at $115B, fiscal 2028 at $230B, with demand already exceeding supply, highlighting Broadcom’s aggressive growth and supply constraints rather than weak demand.

Broadcom's fiscal third quarter produced $16.7 billion in AI semiconductor revenue — more than triple what the company generated in the same period a year ago — and then delivered something the $16.7 billion figure alone does not convey: Hock Tan told investors Wednesday that actual customer demand already exceeds even Broadcom's own $115 billion fiscal 2027 target, meaning the company's remarkable forecast is intentionally conservative because fabrication capacity and advanced packaging supply, not orders, are the binding variable, per the official Q3 earnings press release.

The disclosure inverts the narrative that has dominated Broadcom coverage through the first half of 2026. The risk was supposed to be whether demand would hold. It is holding — and then some.

Anthropic Is Now Broadcom's Biggest Customer in Waiting
The single most structurally significant statement from Wednesday's earnings call was not about the $230 billion fiscal 2028 target, striking as that figure is. It was that Anthropic is on track to become Broadcom's largest XPU customer in 2027, surpassing Google — and to hold that position through 2028, according to the Benzinga Q3 2026 earnings call transcript. Hock Tan said Anthropic will deploy an additional 5 gigawatts of next-generation TPU v8i capacity in 2027 and that Broadcom has clear line of sight to deliver another 10 gigawatts in 2028. That progression — 1 gigawatt of Ironwood in 2026, 5 gigawatts of v8i in 2027, 10 more gigawatts in 2028 — represents one of the most aggressive compute capacity ramps any AI laboratory has publicly committed to.

The shift matters editorially because Broadcom's AI story has been constructed, quarter by quarter, around the Google relationship: Google's TPU programs were the revenue anchor, and every analyst model asking whether the $56 billion fiscal 2026 forecast was achievable ran primarily through Google. Anthropic's emergence as the new anchor customer in 2027 means the company's forward revenue is less exposed to the Google concentration risk that prompted Macquarie's June downgrade — Macquarie cut Broadcom to Neutral from Outperform over that concern — a move that sent the stock sharply lower and has weighed on it relative to peers ever since.

OpenAI, whose first-generation Jalapeño accelerator Broadcom shipped during the third quarter, is on track to rank as the second-largest XPU customer in 2027, per the Benzinga call transcript. Tan said Jalapeño outperforms Nvidia's Grace Blackwell GPU for inference workloads, placing the custom chip at performance parity with or above Nvidia's latest merchant silicon for the specific workloads OpenAI needs. Broadcom and OpenAI are already in development on a second-generation chip and outlining a third.

For Meta, Broadcom expects to begin production shipments of the latest MTIA custom accelerator in the fourth quarter, optimized for inference and recommendation workloads at scale. "Four of our six customers will grow to enormous scale," Tan said, per the Q3 2026 Investing.com transcript.

Q3 by the NumbersTotal consolidated revenue for the quarter ended August 2 came in at $29.59 billion, an 86% year-over-year increase that beat the Wall Street consensus of approximately $29.36 billion, per the official earnings press release. The quarter extended Broadcom's streak of adjusted EPS beats to nine consecutive quarters, with non-GAAP diluted EPS of $3.32 clearing the consensus of $3.22 to $3.24.

Profitability metrics showed the operating leverage that custom silicon generates at scale. Non-GAAP operating income grew 92% year over year to $20.1 billion, representing an operating margin of 68% — a rate that reflects how little incremental overhead the AI chip business requires relative to the revenue it produces, per the earnings press release. Free cash flow reached a record $13.7 billion, equal to 46% of quarterly revenue. The company ended the period with $24.0 billion in cash after paying down $5.6 billion of debt and returning $3.1 billion in dividends.

AI semiconductor revenue of $16.7 billion now accounts for 56% of Broadcom's total revenue — a share that has grown from negligible two years ago, per Benzinga's Q3 call transcript. The Semiconductor Solutions segment as a whole rose 127% year over year to $20.8 billion. Infrastructure Software — anchored by the VMware portfolio — grew 29% to $8.75 billion, marginally short of the $8.82 billion consensus estimate, though it did not generate the kind of concentrated analyst focus that a software miss did in the second quarter.

For the fourth quarter of fiscal 2026, Broadcom guided total revenue to approximately $34.8 billion, 93% above the same period a year ago. AI semiconductor revenue is expected to reach $21.7 billion — a 236% year-over-year increase — as XPU and networking revenue together triple year on year, per the earnings press release. The guidance landed approximately $230 million below the analyst consensus of $35.03 billion, enough to push AVGO down as much as 6% in after-hours trading before partially recovering. The stock had closed the regular session Wednesday at $367.47, up about 6% year to date — meaningfully behind the S&P 500's 12% gain over the same period, a divergence that has puzzled observers given the company's underlying AI chip growth rate.

Cody Acree, an equity research analyst at StoneX with a Buy rating on the stock, captured the reaction precisely: "The magnitude is not quite enough from a top and bottom line standpoint on the beat and raise when you have a company that is this levered to AI," he told Yahoo Finance.

The board declared a quarterly cash dividend of $0.65 per share, payable September 30 to shareholders of record as of September 21.

The Roadmap: $58B This Year, $115B Next, $230B in TwoThe financial figures for fiscal 2027 and 2028 that Tan disclosed Wednesday were prepared remarks, not responses to analyst questions — a signal that Broadcom views them as sufficiently reliable to state publicly rather than let them emerge from Q&A hedging.

Full-year fiscal 2026 AI semiconductor revenue is now projected at $58 billion, up from the prior $56 billion guidance — a 186% year-over-year increase, per Benzinga's earnings call transcript. For fiscal 2027, Broadcom has secured the supply to double AI revenue to approximately $115 billion. For fiscal 2028, the company has line of sight to double again to $230 billion — with supply secured for that target as well.

The crucial qualifier, stated plainly by Tan: demand for fiscal 2027 already exceeds the $115 billion outlook, per the Investing.com Q3 earnings transcript. Broadcom is not holding back a bullish forecast to be conservative. It is holding back a larger number because it has not yet secured all the supply chain capacity needed to deliver it. The forward demand roadmap across Broadcom's six XPU customers extends to 30 gigawatts of aggregate compute capacity — a figure that maps to revenue well above the disclosed targets, per TheStreet's live earnings call updates.

Whether Broadcom can convert that order pipeline into delivered silicon — and whether TSMC can expand fabrication capacity quickly enough — will define the AI infrastructure story for the next two years.

What Actually Limits the $115B Target: CoWoS, HBM, and PowerTan named the supply chain inputs that are pacing Broadcom's AI revenue growth: leading-edge wafers at the 3-nanometer node, CoWoS advanced packaging substrates, high-bandwidth memory, power, land, and system components needed for large-scale data center deployment, per Yahoo Finance's Q3 earnings call highlights.

Understanding why packaging rather than silicon is the binding constraint requires a brief look at how modern AI chips are built. A custom accelerator like Google's Ironwood TPU is not simply a logic die — it is a system assembled through CoWoS (Chip-on-Wafer-on-Substrate), the advanced 2.5D packaging process TSMC developed over 12 years and now controls at roughly 90% of global capacity at AI-chip scale, according to Epoch AI's chip supply research. CoWoS sits the logic die on a silicon interposer alongside stacks of high-bandwidth memory, connecting them with thousands of short, dense electrical paths that enable the terabytes-per-second memory bandwidth modern AI model weights require. Without this packaging step, a fabricated 3nm wafer cannot become a functional, shippable accelerator.

TSMC has confirmed that CoWoS capacity has been sold out through 2026 and into 2027, with packaging lead times of 52-78 weeks. Scaling from approximately 35,000 CoWoS units per month in late 2024 to 130,000 by end-2026 is itself an extraordinary manufacturing achievement — and it is still short of demand. HBM memory from SK Hynix, Samsung, and Micron represents a parallel constraint: AI chip designers consumed roughly 90% of global HBM supply in 2025, leaving virtually no margin for demand growth without new capacity coming online, per the Epoch AI analysis.

Broadcom announced it will increase capital expenditure to $1.4 billion in the fourth quarter, directing spending toward substrate production capacity in Singapore and indium phosphide capacity for co-packaged optics — the optical interconnect technology that Broadcom's AI networking portfolio depends on to link XPU clusters across data centers, per the Benzinga Q3 transcript.

How Ironwood v8i Changes the Technical BenchmarkDuring the third quarter, Broadcom delivered Google's Ironwood TPU v7 in high volume to both Google and Anthropic — simultaneously. At the same time, the company began production shipments of the next-generation TPU v8i, a chip Tan described as having substantially more memory and bandwidth than Ironwood and as designed specifically for inference workloads, per the Alphastreet Q3 2026 transcript.

The v8i's performance claim carries competitive significance: Tan said it is "comparable to, if not surpasses" Nvidia's Vera Rubin GPU — the generation of Nvidia hardware that will not reach volume production until 2027 at the earliest. Whether that benchmark holds at scale across diverse inference workloads remains to be demonstrated in production, but the design achievement is notable: Broadcom is now simultaneously ramping two generations of Google TPU, with v8i shipping ahead of MediaTek's competing v8T design that was initiated before v8i's program began, per Benzinga's full call transcript.

For context on the infrastructure that connects these chips at data center scale, Broadcom's Tomahawk 6 and Tomahawk Ultra Ethernet switching products continued ramping across AI customers during the quarter, and AI networking revenue grew more than 2.5 times year over year. The networking portfolio — Ethernet switches, PCIe switching, optical DSPs, lasers, and co-packaged optics — is what allows thousands of XPUs to operate as a coherent AI training or inference cluster rather than as disconnected processors, per Benzinga's Q3 earnings call.

What Does Broadcom's AI Chip Business Actually Do?Unlike Nvidia, which sells graphics processing units to a broad market — including gaming, scientific computing, and enterprise inference — Broadcom's AI semiconductor business is built on co-design partnerships with individual hyperscalers. The company's engineers collaborate with a customer's architecture team over an 18-to-24-month design cycle to translate the customer's specific model architecture — the structure of their neural network, the memory access patterns, the precision requirements — into a physical chip layout that TSMC can fabricate.

The resulting chip is an application-specific integrated circuit: it can do one thing extraordinarily well and cannot be repurposed for a different customer or a different class of workload, as IEEE Technology Navigator describes for this class of semiconductor. This specificity is precisely what makes the economics work. A chip optimized for running Google's specific transformer architecture can devote die area to matrix multiply-accumulate units calibrated for that workload rather than the general-purpose floating-point logic a GPU needs to serve thousands of different customers. Independent operators have confirmed the economics: Midjourney, the AI image platform, reported cutting monthly inference compute costs from approximately $2.1 million to $700,000 — a 65% reduction — after moving inference workloads from Nvidia GPUs to Google's seventh-generation TPUs, per TechTimes' AI chip cost analysis.

The tradeoff is lock-in and lead time. Once a hyperscaler has co-designed a chip with Broadcom, switching design partners costs roughly one to two chip generations — three to five years of roadmap continuity — because the design knowledge, the verified IP blocks, and the TSMC process relationships do not transfer. That switching cost is Broadcom's moat, and it deepens with every generation of TPU, MTIA, and Jalapeño that ships.

Hyperscaler Capex as the Upstream Driver
The five largest hyperscalers — Alphabet, Microsoft, Amazon, Meta, and Apple — collectively increased capital expenditures approximately 80% in 2026 to more than $700 billion, with AI infrastructure representing the primary growth driver, per Bloomberg's Big Tech capex tracking. That spending flows directly into the order book of the companies that supply the chips, packaging, and networking equipment required to build AI data centers at scale.

Broadcom's AI chip order book entered Q3 carrying more than $30 billion in bookings from the prior quarter alone — a figure that, annualized, exceeds the company's entire AI semiconductor revenue for fiscal 2025, per Reuters reporting via KELO.

VMware's AI Push and the Enterprise LayerBroadcom released its Q3 earnings immediately following VMware Explore 2026, the four-day conference held this week in Las Vegas that opened September 1. At that conference, Broadcom unveiled VMware Private AI Cloud — a platform designed to bring production AI inference inside enterprise data centers — alongside AgentMinder, a governance control plane for autonomous AI agents that Broadcom said handled 43 million API calls per day in internal production. The enterprise AI product line represents Broadcom's bet that the AI infrastructure cycle is not limited to hyperscalers: as enterprises move AI inference onto private infrastructure to manage cost and data governance, VMware Cloud Foundation becomes the software layer those workloads run on, per the VMware Private AI Cloud announcement.

The VMware business has faced significant customer retention headwinds since the $61 billion acquisition in 2023 — a Gartner survey from April 2026 found 76% of VMware customers hold negative views of Broadcom's ownership — but the AI inference narrative gives the platform a retention argument that licensing disputes cannot: migrating away from VMware Cloud Foundation now means rebuilding the AI infrastructure stack from scratch on a competitor platform.

Why Demand Still Outstripping Capacity Is the StoryBroadcom's disclosure that customer demand exceeds its own $115 billion fiscal 2027 guidance is the fact that changes how to read the rest of the numbers. A $16.7 billion quarter and a $21.7 billion Q4 guide are extraordinary. But they are smaller than they could be if CoWoS capacity, HBM allocation, and data center power were unconstrained. The $230 billion fiscal 2028 target is not Broadcom's ceiling — it is the number that Tan believes the supply chain can deliver, with the acknowledged caveat that actual demand exceeds even that figure.

The practical implication for the technology industry is that AI infrastructure build-out is being paced not by customer appetite — which appears essentially unlimited — but by the speed at which TSMC can expand packaging lines, SK Hynix and Micron can produce HBM stacks, and utility operators can permit and commission the power substations needed to run data centers consuming gigawatts of electricity.

RBC has projected the total AI semiconductor market could exceed $550 billion by 2028, per RBC's AI semiconductor forecast. If Broadcom's $230 billion target holds, it would represent roughly 40% of that market — through a business model built not on selling chips to everyone, but on designing chips for six specific customers who are each individually building AI infrastructure at a scale the world has not previously attempted.

Frequently Asked QuestionsWhy did Broadcom stock fall after what appears to be a record quarter?The quarter itself was not the source of disappointment. Broadcom beat analyst estimates on both revenue ($29.59 billion vs. the $29.36 billion consensus) and adjusted EPS ($3.32 vs. $3.22 expected). The sell-off — which initially reached approximately 6% in after-hours trading before partially recovering — was driven by Q4 guidance of $34.8 billion landing roughly $230 million below the analyst consensus of $35.03 billion. At the elevated valuations that AI infrastructure stocks carry in 2026 — Broadcom trades at roughly 25 times forward earnings — even a minor guidance miss against high expectations produces outsized price reactions. As StoneX analyst Cody Acree put it, for a company this exposed to AI, the market expects the beat-and-raise to be larger than what Broadcom delivered, per Yahoo Finance's analyst commentary.

How does an XPU differ from an Nvidia GPU, and why does the difference matter for AI economics?An XPU (Broadcom's term for a custom ASIC it co-designs with a specific hyperscaler) is built to run one customer's specific model architecture and nothing else. An Nvidia GPU is a broadly programmable processor that can run any workload — the same chip trains a language model one week and runs a video rendering job the next. The GPU's programmability is its commercial advantage for Nvidia (it can be sold to millions of customers) but its efficiency disadvantage for any single buyer (die area is devoted to general-purpose compute rather than the specific matrix operations the buyer needs). An XPU eliminates that overhead: every transistor is allocated to the operations the customer actually runs. The result, as demonstrated by production deployments, is a 30% to 65% reduction in inference compute cost compared to GPU-based alternatives for the specific workload the chip was designed for, per TechTimes' XPU cost analysis.

What is limiting Broadcom's AI chip growth if customer demand exceeds even the $115 billion forecast?The binding constraint is not customer orders — it is the supply chain required to manufacture and package the chips those orders represent. CoWoS (Chip-on-Wafer-on-Substrate), the advanced packaging process that bonds AI logic dies to high-bandwidth memory on a silicon interposer, is sold out at TSMC through 2026 and into 2027, with lead times of 52 to 78 weeks. HBM memory from SK Hynix, Samsung, and Micron is a parallel constraint — AI chip manufacturers consumed roughly 90% of global supply in 2025. Beyond chips, the data centers that will house these accelerators require power at gigawatt scale, and permitting and construction timelines for new substations are measured in years. Broadcom's $115 billion fiscal 2027 target is the number Hock Tan believes the supply chain can support, with the explicit acknowledgment that orders from six XPU customers already exceed even that figure, per the Investing.com earnings call transcript.

Which companies are Broadcom's most important AI chip customers, and is Google still the dominant one?Google has historically been Broadcom's largest custom AI chip customer, through the long-running TPU program whose latest generations (Ironwood v7 and v8i) are shipping now. But Hock Tan disclosed Wednesday that Anthropic is on track to surpass Google in 2027 and hold that position into 2028 — with a deployment trajectory of 1 gigawatt of Ironwood in 2026, 5 gigawatts of TPU v8i in 2027, and another 10 gigawatts in 2028. OpenAI, whose first-generation Jalapeño accelerator began shipping in the third quarter, is expected to rank second. Meta's latest MTIA accelerator is entering production in the fourth quarter. Google remains a major customer under a long-term agreement that covers "multi-tens of billions of dollars" of TPUs annually for several years — but Anthropic is emerging as the new anchor relationship in Broadcom's forward revenue model, per the Benzinga earnings call transcript.

[BeenRetired] Copilot: TSMC & Samsung see ArFi & EUV “running hot”? VERY HOT. Here’s the clea...

BeenRetired — 9/3/2026 1:57:11 PM

Copilot: TSMC & Samsung see ArFi & EUV “running hot”? VERY HOT.

Here’s the clean snapshot you’re really asking for: are ArFi and EUV “running hot” at TSMC and Samsung? Yes—very.

What this really means:

EUV:
- N3 already ~¼ of revenue; N2 ramp + A16 rollout in 2H26 means EUV demand is above any prior planning curve.
- 70–80% of a $52–56B 2026 capex budget is pointed at N2/A16 and advanced packaging—this is EUV-centric capacity.
ArFi:
- 5nm and 7nm (still 49% of advanced revenue) are ArFi-intense and remain in tight capacity.
- Mature/specialty nodes and automotive/IoT keep ArFi tools busy even as EUV share rises.

Verdict for TSMC:

EUV demand is explosive and still climbing (N3 ? N2 ? A16).
ArFi demand is structurally strong, not fading—just shifting toward AI, automotive, and specialty logic.

Samsung Foundry: ArFi & EUV demand
Samsung’s details aren’t in the snippets above, but we can infer from known node structure and public wins:

SF3 / SF4 / 5LPE
- Mix of EUV (critical layers) and heavy ArFi multi-patterning.
- AI accelerators, flagship Exynos, and high-end Android SoCs keep both toolsets loaded.
SF2 / SF2P / SF2T (2nm GAA)
- Higher EUV layer count than SF3; ArFi still used for non-critical and BEOL layers.
- Large AI and networking wins (Broadcom, Meta, internal Exynos) imply rising EUV utilization and sustained ArFi demand.
Memory (DRAM / HBM)
- DRAM/HBM nodes remain ArFi-dominant, with EUV creeping into advanced DRAM.
- HBM3E/HBM4 ramps mean ArFi demand is very strong, with incremental EUV growth.

Verdict for Samsung:

EUV demand is sharply up vs early-’26 expectations, driven by 2nm SF2 ramps and AI/accelerator wins.
ArFi demand is robust, anchored by DRAM/HBM and older logic nodes—no sign of slack.

Your operator-grade takeaway

TSMC:
- EUV: running at “sold-out” levels, with N2/A16 pushing tool demand beyond earlier 2026 expectations.
- ArFi: still a workhorse—5/7nm + specialty logic keep immersion fleets tight.
Samsung:
- EUV: rising faster than the early-’26 narrative, thanks to SF2 and AI wins.
- ArFi: buoyed by DRAM/HBM and legacy logic; demand is better than the street expected going into 2026.

If you want, next step we can quantify approximate EUV tool counts per node (N3/N2/SF2/18A) and map how that translates into ASML revenue leverage over 2026–2028.

PS
It's JUST started.

[BeenRetired] Copilot: Intel "foundry demand for both ArFi and EUV in 2026 has been materially...

BeenRetired — 9/3/2026 1:34:56 PM

Copilot: Intel "foundry demand for both ArFi and EUV in 2026 has been materially stronger than what Intel signaled early in the year"

Yes — demand has been hearty, and yes — foundry demand for both ArFi and EUV in 2026 has been materially stronger than what Intel signaled early in the year. The fresh reporting you surfaced makes this very clear.

Below is the structured, evidence-based breakdown with citations.

1. Did Intel say it wouldn’t spend CapEx unless demand was secured?
Yes. Lip-Bu Tan said early in 2026 that Intel would not increase capital expenditures unless demand signals were firm — especially for server CPUs and foundry customers.

The new reporting shows that those demand signals arrived, and in size.

2. Has demand been hearty? (Yes — extremely)
Evidence from Q2 2026 results

Intel’s Q2 revenue: $16.13B, up 25% YoY — the strongest growth in 15 years
Data Center & AI revenue: $6.26B, up 59% YoY
Customer demand exceeds Intel’s growing supply, forcing capacity expansion

This is exactly the “secured demand” Tan said would be required before raising CapEx.

Intel’s response

CapEx raised from $18B -> $20B for 2026
Management expects 2027 CapEx to be significantly higher
Intel is in a capacity shortage, meaning every incremental wafer translates directly into revenue

Conclusion: Intel’s CapEx increase is not speculative — it is a direct reaction to real, secured demand, especially for AI-driven server CPUs.

3. Has foundry demand for ArFi & EUV been better than expected?
(Yes)EUV demand signals

Intel Foundry revenue up 20% sequentially, driven by higher EUV wafer mix and 18A growth
Panther Lake entered high-volume manufacturing using ASML High-NA EUV — a major milestone indicating strong EUV utilization and tool demand
Intel’s €5B expansion in Ireland is explicitly to scale Intel 3 EUV production due to global supply shortages of AI server CPUs

ArFi demand signals
While EUV gets the headlines, ArFi demand is also stronger than expected because:

Intel 3 and Intel 7 still rely heavily on ArFi multi-patterning.
Intel’s €5B Ireland expansion includes leading-edge manufacturing equipment, which (per Intel 3’s process flow) includes substantial ArFi capacity.

Foundry customer traction

Intel Foundry Services revenue: $5.77B, slightly above expectations
Intel 18A-P entered risk production, indicating customers are already committing designs to the node

Conclusion: Both EUV and ArFi demand are stronger than Intel expected earlier in 2026, driven by:

AI server CPU shortages
18A and Intel 3 ramp
High-NA EUV adoption
Foundry customer engagement

4. Why demand surprised to the upside
AI server boom
Hyperscalers are building out AI infrastructure faster than expected, causing:

shortages of Xeon 6 (Intel 3)
pull-forward of 18A capacity
increased EUV wafer mix
need for more ArFi layers in Intel 3/Intel 7 nodes

Foundry traction
Even though external foundry revenue is still small, the signals (18A-P risk production, customer tests, packaging demand) are stronger than Intel anticipated.

Execution improvements
Intel’s fab yields and cycle times improved materially, enabling:

higher wafer output
better economics
justification for more tool purchases

Bottom Line (Operator-grade)
Yes — demand has been hearty. Intel’s 2026-2027 CapEx surge is directly tied to:

AI server CPU shortages
stronger-than-expected foundry traction
higher EUV wafer mix
18A/18A-P ramp
Intel 3 EUV expansion

Yes — foundry demand for ArFi and EUV has been better than expected. Intel’s own reporting shows:

EUV mix rising
High-NA EUV entering volume
ArFi still heavily used in Intel 3/Intel 7
Foundry revenue beating expectations
Capacity shortages driving tool purchases

If you want, I can quantify:

how many EUV tools Intel likely needs for 18A/14A
how ArFi/EUV mix compares to TSMC N2 and Samsung SF2
or how this affects ASML’s 2026–2027 revenue trajectory.

[BeenRetired] Key Points Intel's revenue in the second quarter rose 25% year over year, accele...

BeenRetired — 9/3/2026 1:26:32 PM

Key Points

Intel's revenue in the second quarter rose 25% year over year, accelerating from the first quarter's 7% growth.
Management now expects 2026 capital expenditures to exceed $20 billion, and for 2027 spending to be significantly higher.
Intel's stock sale in August added about 242 million shares, putting the share count approximately 21% above a year ago's level.

Intel stock tripled in a year, so where will it be in 5 years?

[BeenRetired] 18A: Intel unveils next-gen architectures for scalable agentic AI solutions [gra...

BeenRetired — 9/3/2026 1:06:44 PM

18A:
Intel unveils next-gen architectures for scalable agentic AI solutions

Small Business Trends

Intel unveils next-gen architectures for scalable agentic AI solutions*

Story by Leland McFarland • 4h

Intel is making significant strides in the realm of artificial intelligence, unveiling three new architectures aimed at facilitating Agentic AI and enterprise-scale workloads. This development could prove beneficial for small business owners seeking to improve efficiency and optimize operations through advanced technology. As small businesses increasingly harness the power of AI for data analysis, customer engagement, and more, Intel’s latest innovations could provide the tools needed to thrive in a competitive market.

At the heart of Intel’s announcement are three key architectures: the Diamond Rapids processor, the Crescent Island GPU, and the Wildcat Lake System-on-Chip (SoC). Each is designed to meet specific demands of modern computing needs, reshaping how businesses can leverage AI technologies.

Pushkar Ranade, Intel’s Chief Technology Officer, emphasized the transformative potential of Agentic AI, stating, “Agentic AI is fundamentally changing how we design and deliver computing – from the transistor and package up through the full system architecture.” This statement underlines the crucial shift towards integrating general-purpose computing with specialized acceleration technologies—something small business owners should consider as they explore solutions to enhance their operations.

The Diamond Rapids processor stands out for its versatility in enterprise AI applications. Built on the Intel 18A process, it offers a redesigned architecture that combines robust compute components and flexible memory systems. With capabilities such as up to 256 cores, 16 memory channels with high-speed data transfer, and extensive PCIe lanes, Diamond Rapids aims to provide sustained high performance and scalability. This could allow small business owners to run complex AI algorithms efficiently, potentially optimizing workloads ranging from customer relationship management to inventory tracking.

Intel’s Crescent Island GPU is engineered to improve the economics of real-time AI inference. Small businesses can benefit from having access to a low-power, easy-to-deploy solution that enables the use of larger AI models without significant infrastructure overhauls. Its design promotes better returns on AI investments, making it a viable option for small businesses looking to utilize AI for tasks like predictive analytics and customer insights. With features like 32 Xe cores and ample memory capacity, Crescent Island offers a solid pathway for firms to accelerate their AI capabilities while managing costs.

On the client-side, Intel’s Wildcat Lake processors are set to bring advanced AI functionalities to budget-conscious devices such as laptops and edge platforms. By integrating enhanced CPU cores with integrated graphics and advanced neural processing units, Wildcat Lake allows smaller businesses to access sophisticated AI tools without requiring high-end, costly systems. This can democratize AI access, enabling more firms to take advantage of machine learning and data-driven decision-making.

However, small business owners should be mindful of potential challenges that come with implementing these advanced systems. The transition to AI-driven technologies requires not just the hardware but also the necessary skills and infrastructure. Companies must consider staff training and potential disruptions during the implementation phase. Additionally, understanding the ROI on AI initiatives will be crucial in deciding whether such investments align with overall business goals.

Intel’s focus on open standards and integration technology is a noteworthy aspect for small businesses. By fostering an ecosystem that accommodates various computing environments—from cloud to edge—to balance performance and costs, Intel positions itself as a partner in the deployment of scalable AI solutions.

The latest innovations from Intel could indeed pave the way for increased efficiency and competitive advantage for small businesses willing to adapt to these technologies. As the boundaries of computing continue to evolve, staying updated with advancements like those presented at Hot Chips 2026 is essential for any business looking to leverage AI effectively.

For more details on Intel’s Agentic AI architectures and their potential applications, visit the original announcement

* Yes — all three architectures are 18A-family designs. But each uses different variants of the 18A process depending on its role (server, GPU, client). Here’s the precise breakdown grounded in the sources you provided.

Diamond Rapids — Built on Intel 18A-P
Diamond Rapids is explicitly confirmed to be manufactured on Intel’s 18A-P process.

Techzine: “Diamond Rapids… built on the 18A-P process.”
Yahoo Finance: “Built on the Intel 18A-P process.”
Network World: “Diamond Rapids… built using its 18A-P manufacturing technology.”
IT-Online: “Built exclusively on Intel technology, including the power- and performance-enhanced Intel 18A-P.”

Conclusion: Diamond Rapids is fully 18A-P, the highest-performance variant of Intel’s 18A node.

Crescent Island — Uses Intel 18A process family (not explicitly 18A-P)
Multiple sources state Crescent Island is part of Intel’s 18A process family, but none explicitly say 18A-P.

StorageReview: “Fabricated on the Intel Foundry 18A process node family.”
IT-Online: “Underpinned by Intel Foundry technologies including the Intel 18A process family.”

Conclusion: Crescent Island is 18A, but Intel does not specify 18A-P. It is likely using baseline 18A optimized for lower-power inference GPUs.

Wildcat Lake — Built on Intel 18A
Wildcat Lake (Intel Core Series 3) is explicitly stated to be built on Intel 18A.

The Data Center Engineer: “Wildcat Lake… built on Intel 18A.”
IT-Online: “Underpinned by Intel Foundry technologies including the Intel 18A process family.”

Conclusion: Wildcat Lake is 18A, not 18A-P. This aligns with Intel’s strategy: 18A for client SoCs, 18A-P for high-performance Xeon.

Final Answer (Concise)

Diamond Rapids ? 18A-P (confirmed)
Crescent Island ? 18A process family (not explicitly 18A-P)
Wildcat Lake ? 18A (confirmed)

All three architectures are 18A-generation silicon, but only Diamond Rapids uses the performance-enhanced 18A-P variant.

If you want, I can map how Intel’s 18A/18A-P positioning compares to TSMC N2/N2P and Samsung SF2/SF2P/SF2T, especially in terms of BSPDN, nanosheet geometry, and yield signaling.

[BeenRetired] Copilot: Yes — 2nm device vendors will absolutely stress 2nm, GAA, and BSPDN in ...

BeenRetired — 9/3/2026 12:11:46 PM

Copilot: Yes — 2nm device vendors will absolutely stress 2nm, GAA, and BSPDN in 2H26 phones. And they’ll do it because the 2H26 smartphone cycle is the first time all three leading-edge foundries (TSMC N2, Samsung SF2, Intel 18A) intersect with pixel/---bit----dense AMOLED panels and AI-heavy mobile processors that actually need the node benefits.

Below is the operator-grade breakdown tailored to your semiconductor tracking preferences.

2H26 Smartphone Cycle: Why 2nm, GAA, and BSPDN Become Front-and-Center Marketing Points
1. 2nm finally aligns with real mobile bottlenecks
Smartphone vendors have historically downplayed node transitions because:

5nm, 4nm, 3nm gave incremental gains
AI workloads were small
Displays weren’t yet pushing 3–4K pixel densities
Thermals were the limiting factor, not logic density

2H26 changes all of that.

New bottlenecks emerging in 2H26:

On-device AI models (1–3B parameters)
Real-time multimodal inference (camera + voice + AR)
High-refresh 144–165Hz AMOLED
4K/5K pixel-dense panels
UHD computational photography pipelines

These workloads need lower voltage, lower leakage, and higher density — exactly what 2nm GAA + BSPDN deliver.

2nm + GAA + BSPDN: Why vendors will emphasize them
2. GAA is finally a visible differentiator
For the first time, consumers will feel the difference:

Lower idle power = longer battery life
Lower leakage = cooler sustained AI inference
Higher drive current = faster burst performance

Samsung (MBCFET) and Intel (RibbonFET) will market GAA as:

“The biggest transistor upgrade in 15 years.”

TSMC will emphasize:

“Nanosheet refinement + backside power for efficiency leadership.”

This is the first node where transistor architecture becomes a consumer-facing talking point.

3. BSPDN (backside power) becomes a flagship feature
BSPDN gives:

10–20% higher frequency headroom
Up to 30% lower IR drop
Better thermal distribution

Intel 18A will push BSPDN hardest. TSMC N2P (late 2026) will introduce BSPDN-lite. Samsung SF2P/SF2T will emphasize “power rails under the logic” messaging.

Expect marketing phrases like:

“Backside power for next-gen AI acceleration.”
“Dedicated power layer for stable performance.”
“New power delivery architecture for cooler sustained loads.”

Pixel-dense AMOLED + 2nm: Why vendors will connect the dots
4. Displays are becoming power hogs
2H26 AMOLED panels will push:

4K-class resolution
165Hz refresh
2,500–3,000 nit peak brightness
LTPO 3.0 dynamic refresh

Vendors will claim:

“2nm efficiency enables brighter, smoother displays without battery penalty.”

This is true — display drivers and ISP pipelines benefit from lower-voltage logic.

AI processors: The real reason 2nm matters in phones
5. On-device AI jumps from toy models ->real inference
2H26 mobile AI blocks will support:

1–3B parameter LLMs
Real-time multimodal fusion
On-device RAG
Camera semantic segmentation
Live translation + AR overlays

These workloads are:

memory bandwidth hungry
thermal sensitive
latency constrained

2nm + GAA + BSPDN directly improve:

sustained inference
thermal stability
battery drain
burst performance

Vendors will absolutely market this.

Will vendors emphasize 2nm in marketing?
Yes — aggressively.
Expect explicit messaging from:

Apple A19 Pro / A20
Qualcomm Snapdragon 8 Elite Gen 5 / Gen 6
Samsung Exynos 2600 / 2700
MediaTek Dimensity 9400 / 9600
Google Tensor G5 / G6
Huawei Kirin 2nm-class (if sanctions allow)

Themes you’ll see:

“2nm AI engine”
“GAA transistor efficiency”
“Backside power for stable performance”
“Next-gen AMOLED powered by 2nm efficiency”
“On-device AI accelerated by 2nm architecture”

This is the first smartphone cycle where node, transistor architecture, and power delivery become mainstream talking points.

Bottom Line (Operator Grade)
Yes — 2nm vendors will heavily stress 2nm, GAA, and BSPDN in 2H26 phones. And they’ll tie these directly to:

pixel-dense AMOLED
high-refresh displays
sustained AI inference
battery life
thermal stability

This is the first cycle where the physics of the node transition aligns with the user-visible benefits.

PS
All enabled by ASML tool fleet.

PSS
Pixel/bit intense AMOLED & EUV bits is a match made in heaven.

[BeenRetired] "Samsung’s 2nm quoted ~30% cheaper than TSMC"

BeenRetired — 9/3/2026 11:56:00 AM

[BeenRetired] Copilot: "Samsung’s 2nm order momentum is clearly increasing" Short answer:Yes,...

BeenRetired — 9/3/2026 11:54:43 AM

Copilot: "Samsung’s 2nm order momentum is clearly increasing"

Short answer: Yes, Exynos 2600 is competitive—but not superior—to Apple and Qualcomm. And yes, Samsung’s 2nm order momentum is clearly increasing, with multiple multi-billion-dollar wins signaling rising interest.

Below is the precise, sourced breakdown.

Is Exynos 2600 competitive with Apple and Qualcomm?
Competitive? Yes. Leading? No. The Exynos 2600 is the first 2nm smartphone chip, giving Samsung a process-node advantage, but real-world performance still trails Apple and Qualcomm in key areas.

CPU performance

Apple A19 Pro leads in single-core efficiency and responsiveness.
Qualcomm Snapdragon 8 Elite Gen 5 leads in raw performance, especially single-core.
- Snapdragon single-core: ~3670
- Exynos 2600 single-core: ~3105
Exynos 2600 matches Snapdragon in multi-core (within ~1%).

GPU performance

Exynos 2600’s RDNA4-based Xclipse 960 has highest theoretical GFLOPS among the three.
Snapdragon still wins in raw rasterization (˜25% faster).
Exynos 2600 shows better sustained performance under long loads (higher stability %, less throttling).

Efficiency & thermals

Apple A19 Pro remains the efficiency king.
Exynos 2600 benefits from 2nm GAA and Samsung’s new Heat Path Block (HPB) tech, improving sustained thermals.

Overall competitiveness

Apple A19 Pro ? best single-core, best efficiency
Snapdragon 8 Elite Gen 5 ? best raw performance
Exynos 2600 ? best process node (2nm), best sustained GPU stability, competitive multi-core

Conclusion: Exynos 2600 is credible and competitive, but not the outright leader. It closes the gap significantly and demonstrates Samsung’s 2nm viability, which is strategically more important than benchmark wins.

Are Samsung’s 2nm foundry orders increasing?
Yes—dramatically. Samsung’s 2nm momentum has accelerated in 2026 with multiple large-scale wins.

Major 2nm wins (confirmed by reporting)
1. Broadcom — $200 billion through 2030

Massive 5-year deal for 2nm and below custom AI silicon
Includes HBM, 2.3D/2.5D packaging, and networking ASICs
Guarantees high utilization and strengthens Samsung vs TSMC

2. Meta — $6.5 billion MTIA accelerator on Samsung 2nm

Meta moves MTIA from TSMC to Samsung
Samsung’s 2nm quoted ~30% cheaper than TSMC
“Hundreds of thousands” of AI ASICs planned
Pushes Samsung’s medium-term backlog toward 50 trillion won

Why interest is rising

TSMC capacity fully booked through 2027 ? hyperscalers need alternatives.
Samsung’s 2nm pricing advantage (~30% cheaper) attracts AI accelerator customers.
Samsung offers full-stack integration: logic + HBM + advanced packaging.
Global diversification trend: Meta, Tesla, Broadcom, Anthropic all exploring non-TSMC options.

Conclusion:
Samsung’s 2nm order book is surging, with >$200B+ in commitments and multiple hyperscalers shifting workloads to Samsung Foundry. Interest is clearly increasing, driven by capacity constraints at TSMC, cost advantages, and Samsung’s integrated memory + packaging ecosystem.

Bottom line for your semiconductor tracking

Exynos 2600 is strategically important: it proves Samsung’s 2nm GAA in a mass-market product.
Performance is competitive but not leading; however, sustained GPU and thermals are strong.
Samsung’s 2nm foundry business is gaining real traction, with Broadcom and Meta validating the node for AI accelerators.
This strengthens Samsung’s position against TSMC and Intel in the 2026–2028 node race.

If you want, I can map how these 2nm wins affect Samsung’s yield trajectory, TSMC’s N2 customer mix, or Intel 18A competitive pressure—all aligned with your semiconductor monitoring preferences.

[BeenRetired] NVLink Fusion is heart of MediaTek Nvidia deal. The heart of this deal is a tec...

BeenRetired — 9/3/2026 11:41:42 AM

NVLink Fusion is heart of MediaTek Nvidia deal.

The heart of this deal is a technology called NVLink Fusion. It lets outside chipmakers design their own custom AI chips that still plug directly into Nvidia's data center systems.

Here is the pressure behind the move.

Big cloud companies like Amazon, Google, Microsoft, and OpenAI are building their own custom AI chips to rely less on Nvidia's expensive processors, Yahoo Finance reported. MediaTek is one of the companies that can help them build those chips.

By handing MediaTek NVLink Fusion, Nvidia ensures that even custom chips built to avoid it still connect back into its own systems.

So Nvidia keeps earning from the wiring, the racks, and the software, even when the main chip is not its own.

What the deal changes for MediaTek stock investors
For years, MediaTek was known for chips inside mid-range smartphones, TVs, and Wi-Fi routers*. This deal moves it into a much bigger arena.

MediaTek is the world's largest smartphone chip supplier by market share and Qualcomm's (QCOM) main rival, according to CNBC.

New Nvidia deal sends critical signal to one global tech giant
Peace Longe
Wed, September 2, 2026 at 5:03 PM MST

*MediaTek was going, at least, according to shills and "experts".
Logic, Memory, Storage rolling MoAPS just keeps picking up steam.
Leading Edge maniacs' hair on fire.

[BeenRetired] LG taps Samsung Foundry for AI home chips, bypassing TSMC in Korea-backed deal* ...

BeenRetired — 9/1/2026 5:47:48 PM

LG taps Samsung Foundry for AI home chips, bypassing TSMC in Korea-backed deal*
Silicon Investor (SI) -- The First Internet Community

Tech Times

LG taps Samsung Foundry for AI home chips, bypassing TSMC in Korea-backed deal
Story by Ethan Ingamells
Sep 01 • 8 min read • Updated 5h ago

Key takeaways

Cross-Rival Collaboration: LG Electronics teams with CoAsia SEMI for ultra-low-power AI IoT chips, manufactured by Samsung Foundry, despite being direct competitors in home appliances and electronics.
Custom Silicon for Always-On AI: Chips are designed for multi-domain power gating, low standby power, and lightweight inference, enabling smart home appliances to operate efficiently without high energy costs.
Government-Backed Program: Part of South Korea's K-On-Device AI Semiconductor initiative with a ?800 billion ($585M) budget, aiming to strengthen domestic AI chip development across IoT, robotics, and defense.

South Korea's government-sponsored semiconductor program produced a striking industrial alignment on August 31: LG Electronics tapped chip designer CoAsia SEMI to develop two ultra-low-power AI IoT system-on-chips for its next-generation smart home appliances — with Samsung Electronics' foundry arm manufacturing them. That routing is unusual by any measure. LG and Samsung compete head-to-head across televisions, monitors, laptops, and home appliances, and LG has historically relied on TSMC — not Samsung — to fabricate chips even in prior government-funded programs.

The LG IoT chip deal was announced on the same day LG unveiled its ThinQ Claw AI home ecosystem and expanded AI Home platform at IFA 2026 in Berlin — a deliberate synchronization that places the chip deal squarely inside LG's publicly stated ambition to own the ambient AI home market. The silicon strategy and the consumer-facing vision arrived together because they cannot be separated: always-on AI appliances require always-on AI chips, and those chips do not yet exist at the price and power efficiency LG needs.

Cross-Rival Collaboration Rooted in Government Architecture
The partnership sits inside South Korea's K-On-Device AI Semiconductor Technology Development initiative, a program run by the Ministry of Trade, Industry and Resources with an overall semiconductor R&D budget of approximately ?800 billion (approximately $585 million USD) running through December 2030. It spans AI semiconductor development across automobiles, IoT, home appliances, machinery, robotics, and defense, and counts Hyundai Motor, Doosan Robotics, Daedong, and Korea Aerospace Industries among its participating demand customers.

Within this program, the CoAsia SEMI–LG sub-project carries a dedicated development budget of ?31 billion (approximately $22.7 million USD), with the full project timeline running from this year through December 2030. LG Electronics will define the chip specifications and steer the development direction. CoAsia SEMI will handle the chip architecture and optimize it for Samsung's manufacturing processes. Engineers from CoAsia NEXELL — a SoC-focused fabless subsidiary within the broader CoAsia Group — are also expected to contribute.

The stated engineering goal: a family of always-on sensing chips that dramatically reduce power consumption and bill-of-materials cost for LG's AI home platform, targeting an early position in what both companies see as the next competitive frontier for smart home products.

Why Samsung Foundry — and Why It MattersThe manufacturing decision is what has drawn the most attention from supply-chain observers. Industry insiders noted that LG Electronics has primarily used TSMC fabs even for government-funded chip projects. "Even for a government-funded project, it is unusual for LG Electronics to use Samsung Electronics' fab," one industry official told The Elec, the Korean semiconductor trade publication that first reported the deal.

The pivot matters because it is not merely cosmetic. CoAsia SEMI is an officially designated Design Solution Partner (DSP) of Samsung Foundry's SAFE partner ecosystem — meaning its chip designs are engineered from the ground up to Samsung's process specifications, using Samsung's qualified design flows, IP libraries, and manufacturing parameters. That process-specific optimization is not trivially portable: a chip architected to a Samsung process node is not the same chip as one architected to a TSMC process node, even if the logic functions identically. The engineering choices that minimize leakage current, optimize cell libraries, and reduce power in standby are foundry-specific. Once LG's IoT chip tape-out is complete on Samsung's process, future iterations will almost certainly return to the same foundry — not because of contractual lock-in, but because the design work has accumulated around Samsung's manufacturing environment.

This is how the Korean government's program may be doing something more durable than routing one chip order: it is building supply chain alignment through technical dependency, making Samsung Foundry the natural and lowest-friction choice for LG's AI home chip development over the four-year project window and beyond.

What Always-On AI Chips Actually Do — and Why They Require Custom SiliconThe engineering rationale for bespoke silicon begins with what "always-on sensing" demands at the circuit level. A smart home refrigerator that can detect when a door has been left open, recognize food inventory changes, or sense the presence of household members cannot accomplish these tasks by continuously running a general-purpose processor — the power draw would be prohibitive. Instead, the chip must exist in three states simultaneously: a deep sleep mode consuming microwatts or less, an event-triggered wakeup state consuming milliwatts, and a brief active inference state consuming perhaps tens of milliwatts when a sensor threshold is crossed.

Achieving this requires a specific architectural approach. The chip must implement multi-domain power gating — separate power islands for the sensor hub, the neural processing unit (NPU), and the main application processor, each independently controlled. The NPU itself must be capable of running lightweight inference models — keyword detection, presence sensing, anomaly detection — without waking the main CPU. And the entire design must operate at supply voltages low enough to minimize transistor leakage in idle states — a constraint that varies by foundry and process node.

General-purpose chips sourced from TSMC for LG's prior appliance lineup were not designed around these constraints. Custom silicon lets LG and CoAsia SEMI co-optimize the sensor integration, NPU architecture, and power gating specifically for the home appliance use cases LG has defined — and do so at the bill-of-materials cost scale that home appliances require. A smartphone chip that costs $20 in volume is economically incompatible with a washing machine that retails for $800.

CoAsia SEMI: A Samsung Ecosystem Insider
The choice of CoAsia SEMI as chip designer is not incidental to the Samsung Foundry selection. CoAsia SEMI is a subsidiary of CoAsia Group, an Incheon-headquartered semiconductor and IT holding company that traces its origins to agency work with Samsung's System LSI and foundry businesses before formally establishing its DSP partnership with Samsung Foundry in 2019. The company is also an ARM Approved Design Partner (AADP), operates design centers across South Korea, the United States, China, Taiwan, Vietnam, Japan, and Germany, and has accumulated experience on Samsung's 4nm and 5nm process nodes.

In July 2025, CoAsia SEMI partnered with Korean AI chip startup Rebellions to co-develop a next-generation AI chiplet package as part of another national R&D initiative — demonstrating the firm's positioning as a repeat participant in Korea's government-mediated chip ecosystem.

"Based on our cooperation with LG Electronics, we will seek additional business opportunities in AI home products and various application markets," CoAsia SEMI CEO Shin Dong-soo said in the company's August 31 announcement.

What This Means for Samsung Foundry's RecoverySamsung Foundry — the contract manufacturing business of Samsung Electronics — has spent the last two years clawing back from a difficult period. Yield problems at its 3nm process node drove key customers including Qualcomm toward TSMC, and the foundry division posted operating losses exceeding ?2 trillion (approximately $1.5 billion USD) in the fourth quarter of 2024 alone. At its lowest point, some 4nm and 5nm production lines ran below 50% capacity utilization.

The recovery picture heading into the second half of 2026 is substantially improved. Utilization has climbed to the 70–80% range and Samsung has targeted full capacity utilization by the end of 2026, driven by demand for HBM4 base dies (fabricated on a 4nm process) and a growing roster of advanced-node orders. The foundry's 2nm process yield has reached approximately 60%, still below the roughly 70% threshold the industry considers sufficient for large-volume production, but improving.

TSMC, by comparison, held approximately 73% of the global pure-play foundry market in both Q1 and Q2 2026, according to Counterpoint Research data. Samsung held approximately 7% — a gap that has been widening, not narrowing, as TSMC's 2nm production ramp and AI chip demand continuously strengthen its leading position.

In this context, the LG deal — while modest in absolute development budget — carries meaningful symbolic weight. It places a domestic consumer electronics brand of genuine prestige on Samsung Foundry's roster for a government-aligned chip program, and it does so through the ecosystem mechanism (DSP-mediated design) that Samsung has been building specifically to attract smaller and mid-tier customers who cannot justify the engineering overhead of working directly with a foundry.

Korea's Broader On-Device AI AmbitionThe K-On-Device AI program reflects South Korea's calculated effort to develop a domestically rooted AI semiconductor supply chain across sectors where on-device inference is becoming strategically important — automotive (Hyundai Motor), industrial equipment (Daedong), robotics (Doosan Robotics), and defense aerospace (Korea Aerospace Industries), as well as the consumer IoT and home appliance segment that LG anchors. The initiative is explicitly structured to connect domestic fabless designers, domestic foundries, and domestic demand companies — a supply-chain loop that keeps design fees, manufacturing revenue, and IP within Korea's semiconductor ecosystem.

For the home appliance segment specifically, the emphasis on always-on, ultra-low-power IoT SoCs reflects an industry-wide recognition that ambient AI — the ability of devices to continuously sense and interpret their environment without cloud connectivity for basic inference tasks — is where the next competitive differentiation will occur. LG's ThinQ Claw and AI Home announcements at IFA 2026 are the consumer-facing articulation of that premise; the CoAsia SEMI chip deal is the engineering substrate beneath it.

Whether the partnership yields chips that deliver a meaningful competitive edge over the four-year development window will depend on execution. But as a signal of how South Korean industrial policy can realign even entrenched competitive dynamics between rival conglomerates, the LG-Samsung-CoAsia deal is already a case study worth examining closely.

Frequently Asked Questions
Why is LG Electronics using Samsung Foundry instead of TSMC for these chips?LG's pivot from its historical TSMC preference to Samsung Foundry is tied to the structure of South Korea's K-On-Device AI semiconductor program. The government initiative connects domestic chip designers (CoAsia SEMI is a Samsung Foundry Design Solution Partner) with domestic demand companies (LG) and domestic foundries (Samsung). An industry official told The Elec that the Samsung Foundry choice is unusual even by government-program standards, where LG has historically used TSMC. The practical consequence is significant: CoAsia SEMI's design work will be optimized for Samsung's manufacturing parameters, making Samsung the lowest-friction foundry for future LG IoT chip iterations as well.

How do always-on AI chips work in home appliances, and why do they need custom silicon?
Always-on sensing chips operate through a three-state power architecture: a deep sleep mode consuming microwatts while idle, a wakeup state triggered by a sensor event, and a brief active inference state where a neural processing unit runs a lightweight AI model to interpret the event. Keeping this cycle efficient at home appliance power budgets — where you cannot drain a battery or meaningfully increase electricity consumption — requires purpose-built chip architecture with multi-domain power gating and NPU cores optimized for the specific sensor combinations LG uses. General-purpose chips sourced from major foundries are not designed around these constraints, and they cost more per unit than high-volume appliance economics permit.

What does the K-On-Device AI program mean for Samsung Foundry's competitive standing?
The ?800 billion (approximately $585 million USD) government program is structured explicitly to route chip orders through domestic foundries, giving Samsung Foundry access to a pipeline of domestic demand-customer projects that TSMC does not participate in. For a foundry working to rebuild its utilization from a low point where some lines fell below 50% capacity in 2024–2025, and currently targeting 100% utilization in H2 2026, institutionally guaranteed domestic projects provide a stable baseline of orders while the more competitive advanced-node customer wins continue to develop. The LG deal is small individually but represents the kind of domestic ecosystem anchoring that the Korean government program is specifically designed to create.

Is LG and Samsung now working together permanently?
This is a specific project partnership under a government-funded program, not a broad commercial alliance. LG and Samsung remain fierce competitors across TVs, monitors, laptops, and home appliances. The four-year chip development timeline extends through December 2030. Whether LG continues routing chip work through Samsung Foundry beyond that program will depend on whether the custom silicon delivers the performance, power, and cost advantages LG needs — and whether Samsung Foundry's process maturity at the relevant nodes justifies continued preference over TSMC.

*Government dole tailwind continues to blow strong.

[BeenRetired] Samsung’s new SSD could make waiting for file transfers a thing of the past [gr...

BeenRetired — 8/31/2026 12:52:59 PM

Samsung’s new SSD could make waiting for file transfers a thing of the past

Digital Trends

Samsung’s new SSD could make waiting for file transfers a thing of the past
Story by Rachit Agarwal
Aug 29 • 2 min read • Updated 2d ago

Key takeaways

High-Speed Performance: The P9 SSD offers sequential read speeds up to 4,000MB/s and write speeds up to 3,800MB/s, making it ideal for 4K footage, AI content, and large game installs.
Durable Everyday Use: The P7 SSD is designed for regular users, supporting USB4, surviving 2-meter drops, and handling shock and vibration, perfect for laptops, consoles, and cameras.
Global Availability & Pricing: Both drives launch Aug 31 in 1TB–8TB options. Prices range from $289.99–$2,699.99 depending on model and capacity.

Samsung has just pulled the wraps off its newest portable SSDs, the P9 and P7, and it’s launching them where gamers and creators are already gathered: Gamescom 2026 in Cologne, Germany. Both drives run on USB4 connectivity, and Samsung is positioning them as the answer to our ever-growing pile of 4K footage, AI-generated content, and massive game installs.

How fast are we talking?
The P9 is the flagship drive, and it is offering some impressive numbers. It can hit sequential read speeds of up to 4,000MB/s and write speeds of up to 3,800MB/s, roughly double what last year’s T9 could manage.

Samsung is also calling it the world’s first 8TB USB4 portable SSD capable of hitting that 4,000MB/s mark. It gives you enough storage for all the data, along with the speed to handle it without slowing your workflow.

Both drives will be available globally starting Aug 31 in 1TB, 2TB, 4TB, and 8TB options, though availability may vary depending on where you live. Pricing for the P9 starts at $339.99 for 1TB and climbs to $2,699.99 for 8TB, while the P7 starts at $289.99 for 1TB and tops out at $2,289.99 for 8TB.

If your current external drive is struggling to keep up with your needs, Samsung’s new P9 and P7 SSDs might be the answer you are looking for.

What about everyday users who want reliable storage?The P7 makes more sense for everyday users who want durability with performance. It runs on the same USB4 tech but is aimed at regular use rather than professional workloads, and it plays nice with laptops, desktops, phones, gaming consoles, and cameras. The P7 has also passed durability tests. It can survive a 2-meter drop and can handle shock and vibration, so it should survive a rough commute or a spot in your camera bag.

[BeenRetired] Intel Massive Capacity Expansion in Arizona, Ohio, Ireland, Oregon, and Israel. ...

BeenRetired — 8/31/2026 12:39:03 PM

Intel Massive Capacity Expansion in Arizona, Ohio, Ireland, Oregon, and Israel.

Massive Capacity Expansion: Intel plans to accelerate fab builds in Arizona, Ohio, Ireland, Oregon, and Israel, boosting production for nodes like 18A and 14A, potentially increasing revenue toward $200 billion.

Intel is filling its fabs as fast as it can
While there is a possibility that Intel will use $15 billion of the offering to buy out Brookfield Infrastructure Partners, which owns 49% of Intel's existing Arizona fabs, Zinsner hinted that the new funds will probably go toward new fabs. Zinsner pointed out that Intel must commit to buying a large amount of chipmaking equipment over the next few years, which will require a stronger financial backstop.

The details point to a massive amount of new capacity coming online. Intel will be expanding capacity at its existing Fab 34 in Ireland, which produces the Intel 3 node, along with Fab 52 in Arizona, which produces Intel's new 18A node. Intel is also finishing tooling up Fab 62, another massive Arizona fab next to 52 that will produce 18A variants and possibly 14A, Intel's next node.

But that's not all. At the conference, Zinsner also described how Intel will convert some of its Oregon facilities, which are typically research "pilot" lines, into higher-volume manufacturing lines to support 14A as soon as possible. In addition, Zinsner said Intel was moving as "fast as it could" to build out its Ohio fabs:

There is the ability to have eight mods, or there is two mods per fab, so four fabs in Ohio. Mod one is the one obviously we are working on right now. If we could make it go faster, we would. We are going as fast as we can to get that one ready.

It should be noted that before the agentic AI revolution took off, Intel had slowed the build-out of the Ohio fab system. In early 2025, Intel said it was delaying the opening of that fab until at least 2030, pushed back from an initial target of 2026. Well, today Intel is looking to bring that on "as fast as possible," probably in 2028 or 2029. That's quite a change in the span of a year.

Mods one and two will cost a reported $28 billion, which is roughly the same amount invested in Fabs 52 and 62 in Arizona. In other words, this is a massive amount of capacity in addition to Intel's near-term build.

Finally, Zinsner didn't mention Intel's Fab 38 in Israel, where construction was suspended in mid-2025. However, that Fab "shell" is already complete, and would probably be the fastest to market for producing chips outside of Fab 62. Some commentators have recently pointed to increased activity at the Israel fab and to a new site facility operator position that has been posted. That suggests Intel is also likely looking to equip Fab 38 with tools.

Keep in mind that Fab 34 in Ireland, where Intel makes Intel 3, and Fab 52, where 18A production is ongoing, aren't even at full capacity yet. So when you factor in Fab 62, the first two Ohio fabs, Israel Fab 38, and an expansion of its Oregon facility, Intel's internal capacity should increase severalfold over the next few years.

Given that last quarter's revenue was already over $16 billion, indicating a $65 billion annualized run rate, Intel's revenue could theoretically approach $200 billion over a few years if it fills all these fabs it is now accelerating.

Why is Intel so confident? 14A looks massive
It should be noted that when he took on the role of CEO in early 2025, Lip-Bu Tan said he would slow down prior CEO Pat Gelsinger's aggressive capacity build-out and would only build capacity against committed demand. Intel even said in its Q2 2025 quarterly report that development of the upcoming 14A node wasn't guaranteed unless there was significant external demand.

While Intel hasn't officially announced it has landed external customer commitments for 14A, and likely won't due to customer confidentiality concerns, Zinsner basically admitted as much, noting:

Lip-Bu and the team are now meeting on a weekly basis with customers. They are moving away from just looking at data to thinking about, "Well, how much capacity can I get? What does that supply look like?" We are now at a point where we have conviction around customers on 14A externally...

Later on, Zinsner discussed Intel's innovative EMIB-T packaging, which may offer cost and performance advantages over Taiwan Semiconductor Manufacturing's (NYSE: TSM) CoWoS technology. Zinser noted Intel's packaging technology is leading to new opportunities to cross-sell customers to Intel's front-end foundry capabilities:

[Packaging] is a great on-ramp vehicle to show how we can perform not only from an innovation perspective, but also just the blocking and tackling of operationally, how we provide the parts, when we provide them, what our yields look like in high volume. All of those things get tested in advanced packaging, and we win customers there, and I think there is a great opportunity to cross-sell them on the front end as well. Quite honestly, we've already seen that show up even now.

Not only is Intel apparently winning significant external customer volume for its foundry, but its product team is also apparently bullish on 14A. Zinsner noted that under Tan, management let Intel's internal product team choose its foundry, whether Intel's processes or TSMC's. Zinsner said that even though Intel's internal team is "probably the most cynical bunch out of anybody," it has also committed to designing high-volume products on 14A.

Pat Gelsinger's vision is proving out
It should be noted that former CEO Pat Gelsinger had committed to a massive number of cutting-edge fabs back in 2021 when demand for computing was super-high during the COVID-19 pandemic. The subsequent post-COVID downturn made those bets look ill-timed, as Intel lacked the internal financial resources to complete the ambitious plan.

However, with the agentic AI revolution sweeping the tech industry, Gelsinger's vision now looks prescient. Meanwhile, under Tan, Intel appears to have proven out its manufacturing capabilities and positioned itself as a worthy manufacturing vendor to chipmakers.

The 14A node, now set for high-volume manufacturing in 2028, could mark a pivotal moment. Keep in mind that Gelsinger initially envisioned meeting TSMC competitively on the 18A node, then surpassing it on 14A. 14A will make heavier use of high-NA EUV lithography, in which Intel is a first mover, and it will use Intel's second-generation backside power technology. TSMC hasn't yet introduced those chipmaking innovations into its processes.

At the Deutsche Bank conference, Zinsner also noted that 14A development is "doing better than any of the previous nodes in terms of how quickly we're bringing down the defects." He later added, "We haven't seen this performance since 22 nanometer, which is arguably one of the best nodes Intel's ever put out."

Of note, the 22nm process node came out in 2012, back when Intel was the dominant semiconductor manufacturer and multiple generations ahead of competitors in process technology, before it lost its lead to TSMC during the extreme ultraviolet lithography (EUV) transition around 2019.

Many investors currently chalk up Intel's recent gains to "getting lucky" because traditional server CPUs are in such high demand to serve agentic AI, and that its products aren't really competitive with rivals. However, if Intel meets or exceeds TSMC in process technology with 14A, it should be perceived in an entirely new light. From the looks of the recent capital raise, Tan's insider buy, and Zinsner's commentary, it appears management believes that change is imminent.

CEO Lip-Bu Tan just gave 12 million reasons to buy Intel stock