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From: BeenRetired9/9/2017 7:55:42 PM
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"Solido Debuts New ML Tool at TSMC OIP!"...................................................................

"One large customer in the automotive space ran PVTMC Verifier on a chip that had already failed in silicon, and the tool correctly identified the failure in just 310 simulations where it previously required 10,000 brute-force Monte Carlo simulations. It replicated their silicon failure even though the customer thought it couldn’t be done."

Using chips to make better chips.

ASML.



Solido Debuts New ML Tool at TSMC OIP!


by
Daniel Nenni View Profile View Forum Posts Private Message View Articles


Published on 09-08-2017 05:00 AM



The TSMC OIP Ecosystem Forum is upon us and what better place to debut a new tool to prevent silicon failures. Solido Design Automation just launched its latest tool - PVTMC Verifier - and will be demonstrating it in their booth at OIP. This is the third product that was developed within its Machine Learning Labs and is available in their Variation Designer suite of products.

Request a Variation Designer demo here:

http://www.solidodesign.com/products...tion-designer/


I will be there as well during the breaks giving away books (Fabless: The Transformation of the Semiconductor Industry AND Mobile Unleashed), SemiWiki pens, and networking with the semiconductor elite, absolutely.





PVTMC Verifier solves a problem that anyone who’s had an unforeseen silicon failure knows well - PVT and statistical effects interact - but no one knew of a solution to this problem that wasn’t extremely expensive or take a long time to complete.

The brute force approach to address PVT+statistical variation requires hundreds of thousands or millions of simulations. For example, a typical netlist at 3 sigma with 45 PVT corners = 26.9K Monte Carlo samples * 45 corners = 1.2 million simulations. This is not possible to complete in a typical production timeframe. Alternatively, running PVT corners, then MC at the worst-case corner, is error prone because in many cases the worst-case PVT at nominal isn’t the worst-case PVT at your target sigma. Circuits would go to silicon where the failure would be found there, resulting in costly re-spins and increased design cycle time.

Using proprietary machine learning technologies, Solido PVTMC Verifier is able to provide brute force level PVT+statistical variation coverage in only 100’s to 1,000’s of simulations.. You load a netlist into the tool, specify the target sigma and PVT corners you want to test at, and PVTMC Verifier is able to fully verify your design across operating conditions and process variation.

Solido already has several of their customers using PVTMC Verifier in production. One large customer in the automotive space ran PVTMC Verifier on a chip that had already failed in silicon, and the tool correctly identified the failure in just 310 simulations where it previously required 10,000 brute-force Monte Carlo simulations. It replicated their silicon failure even though the customer thought it couldn’t be done.

A second IDM customer of Solido’s used PVTMC Verifier on a known problematic circuit with 9 environmental conditions where a failure was already found in silicon test but missed in simulation using their traditional variation-aware tools. They ran PVTMC Verifier and it also found the problem, and it took only 45 minutes (1,050 simulations). They then fixed the design, confirmed it was fixed in silicon, then re-ran PVTMC Verifier. The problem corner was no longer present. What this means is that PVTMC Verifier was fast enough to utilize for verification, it revealed variation problems before going to silicon, and it eliminated failure risk in the verification stage.

Solido PVTMC Verifier is also being utilized for automotive verification to higher sigma. A common flow involves quickly covering all PVT conditions at 5 sigma with PVTMC Verifier, then verifying the worst-case condition with Solido’s High Sigma Monte Carlo (HSMC) to tighten confidence intervals at the worst-case PVT.
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